2364 		if (rd_reg_word(&reg->mailbox12) & BIT_0)  in qla2x00_initialize_adapter()
2502 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2100_pci_config()
2546 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0)  in qla2300_pci_config()
2554 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2564 		rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2569 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0)  in qla2300_pci_config()
2584 	ha->pci_attr = rd_reg_word(&reg->ctrl_status);  in qla2300_pci_config()
2735 				if ((rd_reg_word(&reg->hccr) &  in qla2x00_reset_chip()
2741 			rd_reg_word(&reg->hccr);	/* PCI Posting. */  in qla2x00_reset_chip()
2747 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2751 		rd_reg_word(&reg->fpm_diag_config);	/* PCI Posting. */  in qla2x00_reset_chip()
2756 			rd_reg_word(&reg->fpm_diag_config); /* PCI Posting. */  in qla2x00_reset_chip()
2761 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2780 		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */  in qla2x00_reset_chip()
2784 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2788 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2806 			if ((rd_reg_word(&reg->ctrl_status) &  in qla2x00_reset_chip()
2821 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_chip()
2840 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
2879 	mb[0] = rd_reg_word(mbptr);  in qla_chk_risc_recovery()
2885 			mb[i] = rd_reg_word(mbptr);  in qla_chk_risc_recovery()
2953 	rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
2954 	for (cnt = 10000; rd_reg_word(&reg->mailbox0) != 0 &&  in qla24xx_reset_risc()
2969 	    rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3016 	wd = rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3024 			wd = rd_reg_word(&reg->mailbox0);  in qla24xx_reset_risc()
3039 	     rd_reg_word(&reg->mailbox0));  in qla24xx_reset_risc()
3196 		data = rd_reg_word(&reg->ctrl_status);  in qla2x00_chip_diag()
3876 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
3987 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4249 	rd_reg_word(ISP_RSP_Q_OUT(ha, reg));		/* PCI Posting. */  in qla2x00_config_rings()
4333 	rd_reg_word(&ioreg->hccr);  in qla24xx_config_rings()
4813 		if ((rd_reg_word(&reg->ctrl_status) >> 14) == 1)  in qla2x00_nvram_config()
7424 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
7426 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()