49 		for (i = 0; i < MVS_SOC_PORTS; i++) {  in mvs_64xx_phy_hacks()
51 			mvs_write_port_vsr_data(mvi, i, 0x2F0);  in mvs_64xx_phy_hacks()
55 		mw32(MVS_GBL_PORT_TYPE, 0);  in mvs_64xx_phy_hacks()
56 		for (i = 0; i < mvi->chip->n_phy; i++) {  in mvs_64xx_phy_hacks()
58 			mvs_write_port_vsr_data(mvi, i, 0x90000000);  in mvs_64xx_phy_hacks()
60 			mvs_write_port_vsr_data(mvi, i, 0x50f2);  in mvs_64xx_phy_hacks()
62 			mvs_write_port_vsr_data(mvi, i, 0x0e);  in mvs_64xx_phy_hacks()
131 			printk(KERN_DEBUG "check SRS 0 %08X.\n", tmp);  in mvs_64xx_clear_srs_irq()
137 			printk(KERN_DEBUG "register set 0x%x was stopped.\n",  in mvs_64xx_clear_srs_irq()
151 	mw32(MVS_GBL_CTL, 0);  in mvs_64xx_chip_reset()
170 	mw32(MVS_GBL_CTL, 0);  in mvs_64xx_chip_reset()
181 	while (i-- > 0) {  in mvs_64xx_chip_reset()
191 	return 0;  in mvs_64xx_chip_reset()
244 	if (mvi->pdev && mvi->pdev->revision == 0)  in mvs_64xx_init()
260 	cctl = mr32(MVS_CTL) & 0xFFFF;  in mvs_64xx_init()
296 	mw32(MVS_PCS, 0);		/* MVS_PCS */  in mvs_64xx_init()
301 	tmp &= 0x0000ffff;  in mvs_64xx_init()
302 	tmp |= 0x00fa0000;  in mvs_64xx_init()
322 	for (i = 0; i < mvi->chip->n_phy; i++) {  in mvs_64xx_init()
336 		writel(0x0E008000, regs + 0x000);  in mvs_64xx_init()
337 		writel(0x59000008, regs + 0x004);  in mvs_64xx_init()
338 		writel(0x20, regs + 0x008);  in mvs_64xx_init()
339 		writel(0x20, regs + 0x00c);  in mvs_64xx_init()
340 		writel(0x20, regs + 0x010);  in mvs_64xx_init()
341 		writel(0x20, regs + 0x014);  in mvs_64xx_init()
342 		writel(0x20, regs + 0x018);  in mvs_64xx_init()
343 		writel(0x20, regs + 0x01c);  in mvs_64xx_init()
345 	for (i = 0; i < mvi->chip->n_phy; i++) {  in mvs_64xx_init()
375 	 * the max count is 0x1ff, while our max slot is 0x200,  in mvs_64xx_init()
376 	 * it will make count 0.  in mvs_64xx_init()
378 	tmp = 0;  in mvs_64xx_init()
379 	if (MVS_CHIP_SLOT_SZ > 0x1ff)  in mvs_64xx_init()
380 		mw32(MVS_INT_COAL, 0x1ff | COAL_EN);  in mvs_64xx_init()
384 	tmp = 0x10000 | interrupt_coalescing;  in mvs_64xx_init()
388 	mw32(MVS_TX_CFG, 0);  in mvs_64xx_init()
402 	mw32(MVS_INT_MASK_SRS_0, 0xFFFF);  in mvs_64xx_init()
404 	return 0;  in mvs_64xx_init()
410 		return 0;  in mvs_64xx_ioremap()
446 		if (stat == 0 || stat == 0xffffffff)  in mvs_64xx_isr_status()
447 			return 0;  in mvs_64xx_isr_status()
470 	mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32));  in mvs_64xx_command_active()
471 	mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32));  in mvs_64xx_command_active()
473 		tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3));  in mvs_64xx_command_active()
476 		tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3));  in mvs_64xx_command_active()
491 	tmp = mr32(MVS_PCS) | 0xFF00;  in mvs_64xx_issue_stop()
503 	offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);  in mvs_64xx_free_reg_set()
527 		return 0;  in mvs_64xx_assign_reg_set()
531 	for (i = 0; i < mvi->chip->srs_sz; i++) {  in mvs_64xx_assign_reg_set()
534 		offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);  in mvs_64xx_assign_reg_set()
545 			return 0;  in mvs_64xx_assign_reg_set()
571 	return 0;  in mvs_64xx_oob_done()
624 	u32 lrmin = 0, lrmax = 0;  in mvs_64xx_phy_set_link_rate()
632 		tmp &= ~(0xf << 8);  in mvs_64xx_phy_set_link_rate()
636 		tmp &= ~(0xf << 12);  in mvs_64xx_phy_set_link_rate()
648 	mw32(MVS_PCS, tmp & 0xFFFF);  in mvs_64xx_clear_active_cmds()
651 	mw32(MVS_CTL, tmp & 0xFFFF);  in mvs_64xx_clear_active_cmds()
686 		dwTmp |= (addr & 0x0003FFFF);  in mvs_64xx_spi_buildcmd()
690 	return 0;  in mvs_64xx_spi_buildcmd()
699 	for (retry = 0; retry < 1; retry++) {  in mvs_64xx_spi_issuecmd()
706 	return 0;  in mvs_64xx_spi_issuecmd()
714 	for (i = 0; i < timeout; i++) {  in mvs_64xx_spi_waitdataready()
717 			return 0;  in mvs_64xx_spi_waitdataready()
732 	for (i = 0; i < MAX_SG_ENTRY - from; i++) {  in mvs_64xx_fix_dma()
742 	u32 tmp = 0;  in mvs_64xx_tune_interrupt()
744 	 * the max count is 0x1ff, while our max slot is 0x200,  in mvs_64xx_tune_interrupt()
745 	 * it will make count 0.  in mvs_64xx_tune_interrupt()
747 	if (time == 0) {  in mvs_64xx_tune_interrupt()
748 		mw32(MVS_INT_COAL, 0);  in mvs_64xx_tune_interrupt()
749 		mw32(MVS_INT_COAL_TMOUT, 0x10000);  in mvs_64xx_tune_interrupt()
751 		if (MVS_CHIP_SLOT_SZ > 0x1ff)  in mvs_64xx_tune_interrupt()
752 			mw32(MVS_INT_COAL, 0x1ff|COAL_EN);  in mvs_64xx_tune_interrupt()
756 		tmp = 0x10000 | time;  in mvs_64xx_tune_interrupt()