Lines Matching +full:reset +full:- +full:assert +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
12 * Add delay after initial bus reset
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
85 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
186 static void mesh_done(struct mesh_state *ms, int start_next);
187 static void mesh_interrupt(struct mesh_state *ms);
188 static void cmd_complete(struct mesh_state *ms);
189 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd);
190 static void halt_dma(struct mesh_state *ms);
191 static void phase_mismatch(struct mesh_state *ms);
213 static void dlog(struct mesh_state *ms, char *fmt, int a) in dlog() argument
215 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in dlog()
218 tlp = &tp->log[tp->log_ix]; in dlog()
219 slp = &ms->log[ms->log_ix]; in dlog()
220 tlp->fmt = fmt; in dlog()
221 tlp->tb = readtb(); in dlog()
222 tlp->phase = (ms->msgphase << 4) + ms->phase; in dlog()
223 tlp->bs0 = ms->mesh->bus_status0; in dlog()
224 tlp->bs1 = ms->mesh->bus_status1; in dlog()
225 tlp->tgt = ms->conn_tgt; in dlog()
226 tlp->d = a; in dlog()
228 if (++tp->log_ix >= N_DBG_LOG) in dlog()
229 tp->log_ix = 0; in dlog()
230 if (tp->n_log < N_DBG_LOG) in dlog()
231 ++tp->n_log; in dlog()
232 if (++ms->log_ix >= N_DBG_SLOG) in dlog()
233 ms->log_ix = 0; in dlog()
234 if (ms->n_log < N_DBG_SLOG) in dlog()
235 ++ms->n_log; in dlog()
238 static void dumplog(struct mesh_state *ms, int t) in dumplog() argument
240 struct mesh_target *tp = &ms->tgts[t]; in dumplog()
244 if (tp->n_log == 0) in dumplog()
246 i = tp->log_ix - tp->n_log; in dumplog()
249 tp->n_log = 0; in dumplog()
251 lp = &tp->log[i]; in dumplog()
253 t, lp->bs1, lp->bs0, lp->phase); in dumplog()
255 printk("tb=%10u ", lp->tb); in dumplog()
257 printk(lp->fmt, lp->d); in dumplog()
261 } while (i != tp->log_ix); in dumplog()
264 static void dumpslog(struct mesh_state *ms) in dumpslog() argument
269 if (ms->n_log == 0) in dumpslog()
271 i = ms->log_ix - ms->n_log; in dumpslog()
274 ms->n_log = 0; in dumpslog()
276 lp = &ms->log[i]; in dumpslog()
278 lp->bs1, lp->bs0, lp->phase, lp->tgt); in dumpslog()
280 printk("tb=%10u ", lp->tb); in dumpslog()
282 printk(lp->fmt, lp->d); in dumpslog()
286 } while (i != ms->log_ix); in dumpslog()
291 static inline void dlog(struct mesh_state *ms, char *fmt, int a) in dlog() argument
293 static inline void dumplog(struct mesh_state *ms, int tgt) in dumplog() argument
295 static inline void dumpslog(struct mesh_state *ms) in dumpslog() argument
303 mesh_dump_regs(struct mesh_state *ms) in mesh_dump_regs() argument
305 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_dump_regs()
306 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_dump_regs()
311 ms, mr, md); in mesh_dump_regs()
314 (mr->count_hi << 8) + mr->count_lo, mr->sequence, in mesh_dump_regs()
315 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count, in mesh_dump_regs()
316 mr->exception, mr->error, mr->intr_mask, mr->interrupt, in mesh_dump_regs()
317 mr->sync_params); in mesh_dump_regs()
318 while(in_8(&mr->fifo_count)) in mesh_dump_regs()
319 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo)); in mesh_dump_regs()
321 in_le32(&md->status), in_le32(&md->cmdptr)); in mesh_dump_regs()
323 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr); in mesh_dump_regs()
325 ms->dma_started, ms->dma_count, ms->n_msgout); in mesh_dump_regs()
327 tp = &ms->tgts[t]; in mesh_dump_regs()
328 if (tp->current_req == NULL) in mesh_dump_regs()
331 t, tp->current_req, tp->data_goes_out, tp->saved_ptr); in mesh_dump_regs()
341 (void)in_8(&mr->mesh_id); in mesh_flush_io()
348 static void mesh_completed(struct mesh_state *ms, struct scsi_cmnd *cmd) in mesh_completed() argument
350 (*cmd->scsi_done)(cmd); in mesh_completed()
355 * and eventually do the initial bus reset. The lock must not be
358 static void mesh_init(struct mesh_state *ms) in mesh_init() argument
360 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_init()
361 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_init()
366 /* Reset controller */ in mesh_init()
367 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_init()
368 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_init()
369 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_init()
370 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_init()
373 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_init()
374 out_8(&mr->source_id, ms->host->this_id); in mesh_init()
375 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_init()
376 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
379 printk(KERN_INFO "mesh: performing initial bus reset...\n"); in mesh_init()
381 /* Reset bus */ in mesh_init()
382 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_init()
385 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_init()
393 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ in mesh_init()
394 out_8(&mr->sequence, SEQ_FLUSHFIFO); in mesh_init()
397 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
398 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_init()
400 ms->phase = idle; in mesh_init()
401 ms->msgphase = msg_none; in mesh_init()
405 static void mesh_start_cmd(struct mesh_state *ms, struct scsi_cmnd *cmd) in mesh_start_cmd() argument
407 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_start_cmd()
410 id = cmd->device->id; in mesh_start_cmd()
411 ms->current_req = cmd; in mesh_start_cmd()
412 ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE; in mesh_start_cmd()
413 ms->tgts[id].current_req = cmd; in mesh_start_cmd()
419 for (i = 0; i < cmd->cmd_len; ++i) in mesh_start_cmd()
420 printk(" %x", cmd->cmnd[i]); in mesh_start_cmd()
425 if (ms->dma_started) in mesh_start_cmd()
428 ms->phase = arbitrating; in mesh_start_cmd()
429 ms->msgphase = msg_none; in mesh_start_cmd()
430 ms->data_ptr = 0; in mesh_start_cmd()
431 ms->dma_started = 0; in mesh_start_cmd()
432 ms->n_msgout = 0; in mesh_start_cmd()
433 ms->last_n_msgout = 0; in mesh_start_cmd()
434 ms->expect_reply = 0; in mesh_start_cmd()
435 ms->conn_tgt = id; in mesh_start_cmd()
436 ms->tgts[id].saved_ptr = 0; in mesh_start_cmd()
437 ms->stat = DID_OK; in mesh_start_cmd()
438 ms->aborting = 0; in mesh_start_cmd()
440 ms->tgts[id].n_log = 0; in mesh_start_cmd()
441 dlog(ms, "start cmd=%x", (int) cmd); in mesh_start_cmd()
445 dlog(ms, "about to arb, intr/exc/err/fc=%.8x", in mesh_start_cmd()
446 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
447 out_8(&mr->interrupt, INT_CMDDONE); in mesh_start_cmd()
448 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
452 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
454 * Some other device has the bus or is arbitrating for it - in mesh_start_cmd()
457 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x", in mesh_start_cmd()
458 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
459 mr->error, mr->fifo_count)); in mesh_start_cmd()
460 for (t = 100; t > 0; --t) { in mesh_start_cmd()
461 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0) in mesh_start_cmd()
463 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
464 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x", in mesh_start_cmd()
465 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
466 mr->error, mr->fifo_count)); in mesh_start_cmd()
467 mesh_interrupt(ms); in mesh_start_cmd()
468 if (ms->phase != arbitrating) in mesh_start_cmd()
473 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
475 ms->stat = DID_BUS_BUSY; in mesh_start_cmd()
476 ms->phase = idle; in mesh_start_cmd()
477 mesh_done(ms, 0); in mesh_start_cmd()
483 * Apparently the mesh has a bug where it will assert both its in mesh_start_cmd()
486 out_8(&mr->dest_id, mr->source_id); in mesh_start_cmd()
497 * is trying to reselect us, reset the mesh and then enable in mesh_start_cmd()
500 out_8(&mr->sequence, SEQ_DISRESEL); in mesh_start_cmd()
501 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
502 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x", in mesh_start_cmd()
503 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
504 mr->error, mr->fifo_count)); in mesh_start_cmd()
505 mesh_interrupt(ms); in mesh_start_cmd()
506 if (ms->phase != arbitrating) in mesh_start_cmd()
508 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x", in mesh_start_cmd()
509 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
510 mr->error, mr->fifo_count)); in mesh_start_cmd()
513 out_8(&mr->sequence, SEQ_ARBITRATE); in mesh_start_cmd()
515 for (t = 230; t > 0; --t) { in mesh_start_cmd()
516 if (in_8(&mr->interrupt) != 0) in mesh_start_cmd()
520 dlog(ms, "after arb, intr/exc/err/fc=%.8x", in mesh_start_cmd()
521 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
522 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
523 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
524 /* looks like a reselection - try resetting the mesh */ in mesh_start_cmd()
525 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x", in mesh_start_cmd()
526 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
527 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_start_cmd()
530 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
531 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
532 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
534 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t) in mesh_start_cmd()
536 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x", in mesh_start_cmd()
537 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
539 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
540 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
547 * reset the bus. in mesh_start_cmd()
558 static void mesh_start(struct mesh_state *ms) in mesh_start() argument
562 if (ms->phase != idle || ms->current_req != NULL) { in mesh_start()
563 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)", in mesh_start()
564 ms->phase, ms); in mesh_start()
568 while (ms->phase == idle) { in mesh_start()
570 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) { in mesh_start()
573 if (ms->tgts[cmd->device->id].current_req == NULL) in mesh_start()
577 next = (struct scsi_cmnd *) cmd->host_scribble; in mesh_start()
579 ms->request_q = next; in mesh_start()
581 prev->host_scribble = (void *) next; in mesh_start()
583 ms->request_qtail = prev; in mesh_start()
585 mesh_start_cmd(ms, cmd); in mesh_start()
589 static void mesh_done(struct mesh_state *ms, int start_next) in mesh_done() argument
592 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in mesh_done()
594 cmd = ms->current_req; in mesh_done()
595 ms->current_req = NULL; in mesh_done()
596 tp->current_req = NULL; in mesh_done()
598 set_host_byte(cmd, ms->stat); in mesh_done()
599 set_status_byte(cmd, cmd->SCp.Status); in mesh_done()
600 if (ms->stat == DID_OK) in mesh_done()
601 scsi_msg_to_host_byte(cmd, cmd->SCp.Message); in mesh_done()
604 cmd->result, ms->data_ptr, scsi_bufflen(cmd)); in mesh_done()
607 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3) in mesh_done()
608 && cmd->request_buffer != 0) { in mesh_done()
609 unsigned char *b = cmd->request_buffer; in mesh_done()
615 cmd->SCp.this_residual -= ms->data_ptr; in mesh_done()
616 mesh_completed(ms, cmd); in mesh_done()
619 out_8(&ms->mesh->sequence, SEQ_ENBRESEL); in mesh_done()
620 mesh_flush_io(ms->mesh); in mesh_done()
622 ms->phase = idle; in mesh_done()
623 mesh_start(ms); in mesh_done()
627 static inline void add_sdtr_msg(struct mesh_state *ms) in add_sdtr_msg() argument
629 int i = ms->n_msgout; in add_sdtr_msg()
631 ms->msgout[i] = EXTENDED_MESSAGE; in add_sdtr_msg()
632 ms->msgout[i+1] = 3; in add_sdtr_msg()
633 ms->msgout[i+2] = EXTENDED_SDTR; in add_sdtr_msg()
634 ms->msgout[i+3] = mesh_sync_period/4; in add_sdtr_msg()
635 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0); in add_sdtr_msg()
636 ms->n_msgout = i + 5; in add_sdtr_msg()
639 static void set_sdtr(struct mesh_state *ms, int period, int offset) in set_sdtr() argument
641 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in set_sdtr()
642 volatile struct mesh_regs __iomem *mr = ms->mesh; in set_sdtr()
645 tp->sdtr_state = sdtr_done; in set_sdtr()
648 if (SYNC_OFF(tp->sync_params)) in set_sdtr()
650 ms->conn_tgt); in set_sdtr()
651 tp->sync_params = ASYNC_PARAMS; in set_sdtr()
652 out_8(&mr->sync_params, ASYNC_PARAMS); in set_sdtr()
656 * We need to compute ceil(clk_freq * period / 500e6) - 2 in set_sdtr()
659 v = (ms->clk_freq / 5000) * period; in set_sdtr()
664 tr = (ms->clk_freq + 250000) / 500000; in set_sdtr()
667 v = (v + 99999) / 100000 - 2; in set_sdtr()
670 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000; in set_sdtr()
674 tp->sync_params = SYNC_PARAMS(offset, v); in set_sdtr()
675 out_8(&mr->sync_params, tp->sync_params); in set_sdtr()
677 ms->conn_tgt, tr/10, tr%10); in set_sdtr()
680 static void start_phase(struct mesh_state *ms) in start_phase() argument
683 volatile struct mesh_regs __iomem *mr = ms->mesh; in start_phase()
684 volatile struct dbdma_regs __iomem *md = ms->dma; in start_phase()
685 struct scsi_cmnd *cmd = ms->current_req; in start_phase()
686 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in start_phase()
688 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x", in start_phase()
689 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence)); in start_phase()
690 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in start_phase()
691 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); in start_phase()
692 switch (ms->msgphase) { in start_phase()
697 out_8(&mr->count_hi, 0); in start_phase()
698 out_8(&mr->count_lo, 1); in start_phase()
699 out_8(&mr->sequence, SEQ_MSGIN + seq); in start_phase()
700 ms->n_msgin = 0; in start_phase()
705 * To make sure ATN drops before we assert ACK for in start_phase()
709 if (ms->n_msgout <= 0) { in start_phase()
711 ms->n_msgout); in start_phase()
712 mesh_dump_regs(ms); in start_phase()
713 ms->msgphase = msg_none; in start_phase()
716 if (ALLOW_DEBUG(ms->conn_tgt)) { in start_phase()
718 ms->n_msgout); in start_phase()
719 for (i = 0; i < ms->n_msgout; ++i) in start_phase()
720 printk(" %x", ms->msgout[i]); in start_phase()
723 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0], in start_phase()
724 ms->msgout[1], ms->msgout[2])); in start_phase()
725 out_8(&mr->count_hi, 0); in start_phase()
726 out_8(&mr->sequence, SEQ_FLUSHFIFO); in start_phase()
730 * If ATN is not already asserted, we assert it, then in start_phase()
733 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) { in start_phase()
734 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0); in start_phase()
735 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */ in start_phase()
738 out_8(&mr->count_lo, 1); in start_phase()
739 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
740 out_8(&mr->bus_status0, 0); /* release explicit ATN */ in start_phase()
741 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0); in start_phase()
743 if (ms->n_msgout == 1) { in start_phase()
750 cmd_complete(ms); in start_phase()
752 out_8(&mr->count_lo, ms->n_msgout - 1); in start_phase()
753 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
754 for (i = 0; i < ms->n_msgout - 1; ++i) in start_phase()
755 out_8(&mr->fifo, ms->msgout[i]); in start_phase()
761 ms->msgphase); in start_phase()
764 switch (ms->phase) { in start_phase()
766 out_8(&mr->dest_id, ms->conn_tgt); in start_phase()
767 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN); in start_phase()
770 out_8(&mr->sync_params, tp->sync_params); in start_phase()
771 out_8(&mr->count_hi, 0); in start_phase()
773 out_8(&mr->count_lo, cmd->cmd_len); in start_phase()
774 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
775 for (i = 0; i < cmd->cmd_len; ++i) in start_phase()
776 out_8(&mr->fifo, cmd->cmnd[i]); in start_phase()
778 out_8(&mr->count_lo, 6); in start_phase()
779 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
781 out_8(&mr->fifo, 0); in start_phase()
786 if (!ms->dma_started) { in start_phase()
787 set_dma_cmds(ms, cmd); in start_phase()
788 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds)); in start_phase()
789 out_le32(&md->control, (RUN << 16) | RUN); in start_phase()
790 ms->dma_started = 1; in start_phase()
792 nb = ms->dma_count; in start_phase()
795 ms->dma_count -= nb; in start_phase()
796 ms->data_ptr += nb; in start_phase()
797 out_8(&mr->count_lo, nb); in start_phase()
798 out_8(&mr->count_hi, nb >> 8); in start_phase()
799 out_8(&mr->sequence, (tp->data_goes_out? in start_phase()
803 out_8(&mr->count_hi, 0); in start_phase()
804 out_8(&mr->count_lo, 1); in start_phase()
805 out_8(&mr->sequence, SEQ_STATUS + seq); in start_phase()
809 out_8(&mr->sequence, SEQ_ENBRESEL); in start_phase()
812 dlog(ms, "enbresel intr/exc/err/fc=%.8x", in start_phase()
813 MKWORD(mr->interrupt, mr->exception, mr->error, in start_phase()
814 mr->fifo_count)); in start_phase()
815 out_8(&mr->sequence, SEQ_BUSFREE); in start_phase()
819 ms->phase); in start_phase()
820 dumpslog(ms); in start_phase()
825 static inline void get_msgin(struct mesh_state *ms) in get_msgin() argument
827 volatile struct mesh_regs __iomem *mr = ms->mesh; in get_msgin()
830 n = mr->fifo_count; in get_msgin()
832 i = ms->n_msgin; in get_msgin()
833 ms->n_msgin = i + n; in get_msgin()
834 for (; n > 0; --n) in get_msgin()
835 ms->msgin[i++] = in_8(&mr->fifo); in get_msgin()
839 static inline int msgin_length(struct mesh_state *ms) in msgin_length() argument
844 if (ms->n_msgin > 0) { in msgin_length()
845 b = ms->msgin[0]; in msgin_length()
848 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2; in msgin_length()
850 /* 2-byte message */ in msgin_length()
857 static void reselected(struct mesh_state *ms) in reselected() argument
859 volatile struct mesh_regs __iomem *mr = ms->mesh; in reselected()
864 switch (ms->phase) { in reselected()
868 if ((cmd = ms->current_req) != NULL) { in reselected()
870 cmd->host_scribble = (void *) ms->request_q; in reselected()
871 if (ms->request_q == NULL) in reselected()
872 ms->request_qtail = cmd; in reselected()
873 ms->request_q = cmd; in reselected()
874 tp = &ms->tgts[cmd->device->id]; in reselected()
875 tp->current_req = NULL; in reselected()
879 ms->phase = reselecting; in reselected()
880 mesh_done(ms, 0); in reselected()
886 ms->msgphase, ms->phase, ms->conn_tgt); in reselected()
887 dumplog(ms, ms->conn_tgt); in reselected()
888 dumpslog(ms); in reselected()
891 if (ms->dma_started) { in reselected()
893 halt_dma(ms); in reselected()
895 ms->current_req = NULL; in reselected()
896 ms->phase = dataing; in reselected()
897 ms->msgphase = msg_in; in reselected()
898 ms->n_msgout = 0; in reselected()
899 ms->last_n_msgout = 0; in reselected()
900 prev = ms->conn_tgt; in reselected()
905 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) { in reselected()
908 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
911 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
914 dlog(ms, "extra resel err/exc/fc = %.6x", in reselected()
915 MKWORD(0, mr->error, mr->exception, mr->fifo_count)); in reselected()
917 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
920 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
923 out_8(&mr->sync_params, ASYNC_PARAMS); in reselected()
928 if (in_8(&mr->fifo_count) == 0) { in reselected()
930 ms->conn_tgt = ms->host->this_id; in reselected()
935 b = in_8(&mr->fifo); in reselected()
936 dlog(ms, "reseldata %x", b); in reselected()
937 } while (in_8(&mr->fifo_count)); in reselected()
939 if ((b & (1 << t)) != 0 && t != ms->host->this_id) in reselected()
941 if (b != (1 << t) + (1 << ms->host->this_id)) { in reselected()
943 ms->conn_tgt = ms->host->this_id; in reselected()
951 ms->conn_tgt = t; in reselected()
952 tp = &ms->tgts[t]; in reselected()
953 out_8(&mr->sync_params, tp->sync_params); in reselected()
957 tp->saved_ptr, tp->data_goes_out, tp->current_req); in reselected()
959 ms->current_req = tp->current_req; in reselected()
960 if (tp->current_req == NULL) { in reselected()
964 ms->data_ptr = tp->saved_ptr; in reselected()
965 dlog(ms, "resel prev tgt=%d", prev); in reselected()
966 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception)); in reselected()
967 start_phase(ms); in reselected()
971 dumplog(ms, ms->conn_tgt); in reselected()
972 dumpslog(ms); in reselected()
973 ms->data_ptr = 0; in reselected()
974 ms->aborting = 1; in reselected()
975 start_phase(ms); in reselected()
978 static void do_abort(struct mesh_state *ms) in do_abort() argument
980 ms->msgout[0] = ABORT; in do_abort()
981 ms->n_msgout = 1; in do_abort()
982 ms->aborting = 1; in do_abort()
983 ms->stat = DID_ABORT; in do_abort()
984 dlog(ms, "abort", 0); in do_abort()
987 static void handle_reset(struct mesh_state *ms) in handle_reset() argument
992 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_reset()
995 tp = &ms->tgts[tgt]; in handle_reset()
996 if ((cmd = tp->current_req) != NULL) { in handle_reset()
998 tp->current_req = NULL; in handle_reset()
999 mesh_completed(ms, cmd); in handle_reset()
1001 ms->tgts[tgt].sdtr_state = do_sdtr; in handle_reset()
1002 ms->tgts[tgt].sync_params = ASYNC_PARAMS; in handle_reset()
1004 ms->current_req = NULL; in handle_reset()
1005 while ((cmd = ms->request_q) != NULL) { in handle_reset()
1006 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble; in handle_reset()
1008 mesh_completed(ms, cmd); in handle_reset()
1010 ms->phase = idle; in handle_reset()
1011 ms->msgphase = msg_none; in handle_reset()
1012 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_reset()
1013 out_8(&mr->sequence, SEQ_FLUSHFIFO); in handle_reset()
1016 out_8(&mr->sync_params, ASYNC_PARAMS); in handle_reset()
1017 out_8(&mr->sequence, SEQ_ENBRESEL); in handle_reset()
1023 struct mesh_state *ms = dev_id; in do_mesh_interrupt() local
1024 struct Scsi_Host *dev = ms->host; in do_mesh_interrupt()
1026 spin_lock_irqsave(dev->host_lock, flags); in do_mesh_interrupt()
1027 mesh_interrupt(ms); in do_mesh_interrupt()
1028 spin_unlock_irqrestore(dev->host_lock, flags); in do_mesh_interrupt()
1032 static void handle_error(struct mesh_state *ms) in handle_error() argument
1035 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_error()
1037 err = in_8(&mr->error); in handle_error()
1038 exc = in_8(&mr->exception); in handle_error()
1039 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_error()
1040 dlog(ms, "error err/exc/fc/cl=%.8x", in handle_error()
1041 MKWORD(err, exc, mr->fifo_count, mr->count_lo)); in handle_error()
1043 /* SCSI bus was reset */ in handle_error()
1044 printk(KERN_INFO "mesh: SCSI bus reset detected: " in handle_error()
1046 while ((in_8(&mr->bus_status1) & BS1_RST) != 0) in handle_error()
1049 if (ms->dma_started) in handle_error()
1050 halt_dma(ms); in handle_error()
1051 handle_reset(ms); in handle_error()
1058 reselected(ms); in handle_error()
1061 if (!ms->aborting) { in handle_error()
1063 ms->conn_tgt); in handle_error()
1064 dumplog(ms, ms->conn_tgt); in handle_error()
1065 dumpslog(ms); in handle_error()
1067 out_8(&mr->interrupt, INT_CMDDONE); in handle_error()
1068 ms->stat = DID_ABORT; in handle_error()
1069 mesh_done(ms, 1); in handle_error()
1073 if (ms->msgphase == msg_in) { in handle_error()
1075 ms->conn_tgt); in handle_error()
1076 ms->msgout[0] = MSG_PARITY_ERROR; in handle_error()
1077 ms->n_msgout = 1; in handle_error()
1078 ms->msgphase = msg_in_bad; in handle_error()
1079 cmd_complete(ms); in handle_error()
1082 if (ms->stat == DID_OK) { in handle_error()
1084 ms->conn_tgt); in handle_error()
1085 ms->stat = DID_PARITY; in handle_error()
1087 count = (mr->count_hi << 8) + mr->count_lo; in handle_error()
1089 cmd_complete(ms); in handle_error()
1092 out_8(&mr->sequence, mr->sequence); in handle_error()
1102 reselected(ms); in handle_error()
1108 phase_mismatch(ms); in handle_error()
1116 mesh_dump_regs(ms); in handle_error()
1117 dumplog(ms, ms->conn_tgt); in handle_error()
1118 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) { in handle_error()
1120 do_abort(ms); in handle_error()
1121 phase_mismatch(ms); in handle_error()
1124 ms->stat = DID_ERROR; in handle_error()
1125 mesh_done(ms, 1); in handle_error()
1128 static void handle_exception(struct mesh_state *ms) in handle_exception() argument
1131 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_exception()
1133 exc = in_8(&mr->exception); in handle_exception()
1134 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE); in handle_exception()
1138 reselected(ms); in handle_exception()
1141 ms->stat = DID_BUS_BUSY; in handle_exception()
1142 mesh_done(ms, 1); in handle_exception()
1145 ms->stat = DID_BAD_TARGET; in handle_exception()
1146 mesh_done(ms, 1); in handle_exception()
1150 phase_mismatch(ms); in handle_exception()
1153 mesh_dump_regs(ms); in handle_exception()
1154 dumplog(ms, ms->conn_tgt); in handle_exception()
1155 do_abort(ms); in handle_exception()
1156 phase_mismatch(ms); in handle_exception()
1160 static void handle_msgin(struct mesh_state *ms) in handle_msgin() argument
1163 struct scsi_cmnd *cmd = ms->current_req; in handle_msgin()
1164 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in handle_msgin()
1166 if (ms->n_msgin == 0) in handle_msgin()
1168 code = ms->msgin[0]; in handle_msgin()
1169 if (ALLOW_DEBUG(ms->conn_tgt)) { in handle_msgin()
1170 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin); in handle_msgin()
1171 for (i = 0; i < ms->n_msgin; ++i) in handle_msgin()
1172 printk(" %x", ms->msgin[i]); in handle_msgin()
1175 dlog(ms, "msgin msg=%.8x", in handle_msgin()
1176 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2])); in handle_msgin()
1178 ms->expect_reply = 0; in handle_msgin()
1179 ms->n_msgout = 0; in handle_msgin()
1180 if (ms->n_msgin < msgin_length(ms)) in handle_msgin()
1183 cmd->SCp.Message = code; in handle_msgin()
1188 switch (ms->msgin[2]) { in handle_msgin()
1190 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6] in handle_msgin()
1191 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8); in handle_msgin()
1194 if (tp->sdtr_state != sdtr_sent) { in handle_msgin()
1196 add_sdtr_msg(ms); in handle_msgin()
1199 if (ms->msgout[3] < ms->msgin[3]) in handle_msgin()
1200 ms->msgout[3] = ms->msgin[3]; in handle_msgin()
1201 if (ms->msgout[4] > ms->msgin[4]) in handle_msgin()
1202 ms->msgout[4] = ms->msgin[4]; in handle_msgin()
1203 set_sdtr(ms, ms->msgout[3], ms->msgout[4]); in handle_msgin()
1204 ms->msgphase = msg_out; in handle_msgin()
1206 set_sdtr(ms, ms->msgin[3], ms->msgin[4]); in handle_msgin()
1214 tp->saved_ptr = ms->data_ptr; in handle_msgin()
1217 ms->data_ptr = tp->saved_ptr; in handle_msgin()
1220 ms->phase = disconnecting; in handle_msgin()
1225 if (tp->sdtr_state == sdtr_sent) in handle_msgin()
1226 set_sdtr(ms, 0, 0); in handle_msgin()
1233 do_abort(ms); in handle_msgin()
1234 ms->msgphase = msg_out; in handle_msgin()
1235 } else if (code != cmd->device->lun + IDENTIFY_BASE) { in handle_msgin()
1238 "target %d\n", code - IDENTIFY_BASE, in handle_msgin()
1239 cmd->device->lun, ms->conn_tgt); in handle_msgin()
1249 ms->conn_tgt); in handle_msgin()
1250 for (i = 0; i < ms->n_msgin; ++i) in handle_msgin()
1251 printk(" %x", ms->msgin[i]); in handle_msgin()
1253 ms->msgout[0] = MESSAGE_REJECT; in handle_msgin()
1254 ms->n_msgout = 1; in handle_msgin()
1255 ms->msgphase = msg_out; in handle_msgin()
1261 static void set_dma_cmds(struct mesh_state *ms, struct scsi_cmnd *cmd) in set_dma_cmds() argument
1267 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out? in set_dma_cmds()
1269 dcmds = ms->dma_cmds; in set_dma_cmds()
1274 cmd->SCp.this_residual = scsi_bufflen(cmd); in set_dma_cmds()
1281 off = ms->data_ptr; in set_dma_cmds()
1287 total += scl->length; in set_dma_cmds()
1289 off -= dma_len; in set_dma_cmds()
1294 dcmds->req_count = cpu_to_le16(dma_len - off); in set_dma_cmds()
1295 dcmds->command = cpu_to_le16(dma_cmd); in set_dma_cmds()
1296 dcmds->phy_addr = cpu_to_le32(dma_addr + off); in set_dma_cmds()
1297 dcmds->xfer_status = 0; in set_dma_cmds()
1299 dtot += dma_len - off; in set_dma_cmds()
1310 dcmds->req_count = cpu_to_le16(dtot); in set_dma_cmds()
1311 dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf)); in set_dma_cmds()
1312 dcmds->xfer_status = 0; in set_dma_cmds()
1315 dma_cmd += OUTPUT_LAST - OUTPUT_MORE; in set_dma_cmds()
1316 dcmds[-1].command = cpu_to_le16(dma_cmd); in set_dma_cmds()
1318 dcmds->command = cpu_to_le16(DBDMA_STOP); in set_dma_cmds()
1319 ms->dma_count = dtot; in set_dma_cmds()
1322 static void halt_dma(struct mesh_state *ms) in halt_dma() argument
1324 volatile struct dbdma_regs __iomem *md = ms->dma; in halt_dma()
1325 volatile struct mesh_regs __iomem *mr = ms->mesh; in halt_dma()
1326 struct scsi_cmnd *cmd = ms->current_req; in halt_dma()
1329 if (!ms->tgts[ms->conn_tgt].data_goes_out) { in halt_dma()
1332 while (t > 0 && in_8(&mr->fifo_count) != 0 in halt_dma()
1333 && (in_le32(&md->status) & ACTIVE) != 0) { in halt_dma()
1334 --t; in halt_dma()
1338 out_le32(&md->control, RUN << 16); /* turn off RUN bit */ in halt_dma()
1339 nb = (mr->count_hi << 8) + mr->count_lo; in halt_dma()
1340 dlog(ms, "halt_dma fc/count=%.6x", in halt_dma()
1341 MKWORD(0, mr->fifo_count, 0, nb)); in halt_dma()
1342 if (ms->tgts[ms->conn_tgt].data_goes_out) in halt_dma()
1343 nb += mr->fifo_count; in halt_dma()
1346 ms->data_ptr -= nb; in halt_dma()
1347 dlog(ms, "data_ptr %x", ms->data_ptr); in halt_dma()
1348 if (ms->data_ptr < 0) { in halt_dma()
1349 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n", in halt_dma()
1350 ms->data_ptr, nb, ms); in halt_dma()
1351 ms->data_ptr = 0; in halt_dma()
1353 dumplog(ms, ms->conn_tgt); in halt_dma()
1354 dumpslog(ms); in halt_dma()
1357 ms->data_ptr > scsi_bufflen(cmd)) { in halt_dma()
1360 ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd), in halt_dma()
1361 ms->tgts[ms->conn_tgt].data_goes_out); in halt_dma()
1365 ms->dma_started = 0; in halt_dma()
1368 static void phase_mismatch(struct mesh_state *ms) in phase_mismatch() argument
1370 volatile struct mesh_regs __iomem *mr = ms->mesh; in phase_mismatch()
1373 dlog(ms, "phasemm ch/cl/seq/fc=%.8x", in phase_mismatch()
1374 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count)); in phase_mismatch()
1375 phase = in_8(&mr->bus_status0) & BS0_PHASE; in phase_mismatch()
1376 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) { in phase_mismatch()
1378 out_8(&mr->count_lo, 1); in phase_mismatch()
1379 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in phase_mismatch()
1382 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in phase_mismatch()
1383 ms->msgphase = msg_out_last; in phase_mismatch()
1387 if (ms->msgphase == msg_in) { in phase_mismatch()
1388 get_msgin(ms); in phase_mismatch()
1389 if (ms->n_msgin) in phase_mismatch()
1390 handle_msgin(ms); in phase_mismatch()
1393 if (ms->dma_started) in phase_mismatch()
1394 halt_dma(ms); in phase_mismatch()
1395 if (mr->fifo_count) { in phase_mismatch()
1396 out_8(&mr->sequence, SEQ_FLUSHFIFO); in phase_mismatch()
1401 ms->msgphase = msg_none; in phase_mismatch()
1404 ms->tgts[ms->conn_tgt].data_goes_out = 0; in phase_mismatch()
1405 ms->phase = dataing; in phase_mismatch()
1408 ms->tgts[ms->conn_tgt].data_goes_out = 1; in phase_mismatch()
1409 ms->phase = dataing; in phase_mismatch()
1412 ms->phase = commanding; in phase_mismatch()
1415 ms->phase = statusing; in phase_mismatch()
1418 ms->msgphase = msg_in; in phase_mismatch()
1419 ms->n_msgin = 0; in phase_mismatch()
1422 ms->msgphase = msg_out; in phase_mismatch()
1423 if (ms->n_msgout == 0) { in phase_mismatch()
1424 if (ms->aborting) { in phase_mismatch()
1425 do_abort(ms); in phase_mismatch()
1427 if (ms->last_n_msgout == 0) { in phase_mismatch()
1430 ms->msgout[0] = NOP; in phase_mismatch()
1431 ms->last_n_msgout = 1; in phase_mismatch()
1433 ms->n_msgout = ms->last_n_msgout; in phase_mismatch()
1439 ms->stat = DID_ERROR; in phase_mismatch()
1440 mesh_done(ms, 1); in phase_mismatch()
1444 start_phase(ms); in phase_mismatch()
1447 static void cmd_complete(struct mesh_state *ms) in cmd_complete() argument
1449 volatile struct mesh_regs __iomem *mr = ms->mesh; in cmd_complete()
1450 struct scsi_cmnd *cmd = ms->current_req; in cmd_complete()
1451 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in cmd_complete()
1454 dlog(ms, "cmd_complete fc=%x", mr->fifo_count); in cmd_complete()
1455 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); in cmd_complete()
1456 switch (ms->msgphase) { in cmd_complete()
1459 ms->n_msgin = 0; in cmd_complete()
1460 ms->msgphase = msg_in; in cmd_complete()
1465 get_msgin(ms); in cmd_complete()
1466 n = msgin_length(ms); in cmd_complete()
1467 if (ms->n_msgin < n) { in cmd_complete()
1468 out_8(&mr->count_lo, n - ms->n_msgin); in cmd_complete()
1469 out_8(&mr->sequence, SEQ_MSGIN + seq); in cmd_complete()
1471 ms->msgphase = msg_none; in cmd_complete()
1472 handle_msgin(ms); in cmd_complete()
1473 start_phase(ms); in cmd_complete()
1478 out_8(&mr->sequence, SEQ_FLUSHFIFO); in cmd_complete()
1481 out_8(&mr->count_lo, 1); in cmd_complete()
1482 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg); in cmd_complete()
1497 out_8(&mr->count_lo, 1); in cmd_complete()
1498 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN); in cmd_complete()
1500 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0) in cmd_complete()
1502 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x", in cmd_complete()
1503 MKWORD(mr->error, mr->exception, in cmd_complete()
1504 mr->fifo_count, mr->count_lo)); in cmd_complete()
1505 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) { in cmd_complete()
1507 ms->last_n_msgout = ms->n_msgout; in cmd_complete()
1508 ms->n_msgout = 0; in cmd_complete()
1509 if (in_8(&mr->interrupt) & INT_ERROR) { in cmd_complete()
1511 in_8(&mr->error)); in cmd_complete()
1512 handle_error(ms); in cmd_complete()
1515 if (in_8(&mr->exception) != EXC_PHASEMM) in cmd_complete()
1517 in_8(&mr->exception)); in cmd_complete()
1520 in_8(&mr->bus_status0)); in cmd_complete()
1521 handle_exception(ms); in cmd_complete()
1524 if (in_8(&mr->bus_status0) & BS0_REQ) { in cmd_complete()
1525 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in cmd_complete()
1528 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in cmd_complete()
1529 ms->msgphase = msg_out_last; in cmd_complete()
1531 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN); in cmd_complete()
1532 ms->msgphase = msg_out_xxx; in cmd_complete()
1537 ms->last_n_msgout = ms->n_msgout; in cmd_complete()
1538 ms->n_msgout = 0; in cmd_complete()
1539 ms->msgphase = ms->expect_reply? msg_in: msg_none; in cmd_complete()
1540 start_phase(ms); in cmd_complete()
1544 switch (ms->phase) { in cmd_complete()
1547 dumpslog(ms); in cmd_complete()
1550 dlog(ms, "Selecting phase at command completion",0); in cmd_complete()
1551 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt), in cmd_complete()
1552 (cmd? cmd->device->lun: 0)); in cmd_complete()
1553 ms->n_msgout = 1; in cmd_complete()
1554 ms->expect_reply = 0; in cmd_complete()
1555 if (ms->aborting) { in cmd_complete()
1556 ms->msgout[0] = ABORT; in cmd_complete()
1557 ms->n_msgout++; in cmd_complete()
1558 } else if (tp->sdtr_state == do_sdtr) { in cmd_complete()
1560 add_sdtr_msg(ms); in cmd_complete()
1561 ms->expect_reply = 1; in cmd_complete()
1562 tp->sdtr_state = sdtr_sent; in cmd_complete()
1564 ms->msgphase = msg_out; in cmd_complete()
1573 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) { in cmd_complete()
1574 if (--t < 0) { in cmd_complete()
1575 dlog(ms, "impatient for req", ms->n_msgout); in cmd_complete()
1576 ms->msgphase = msg_none; in cmd_complete()
1583 if (ms->dma_count != 0) { in cmd_complete()
1584 start_phase(ms); in cmd_complete()
1597 out_8(&mr->sequence, 0); in cmd_complete()
1598 out_8(&mr->interrupt, in cmd_complete()
1600 halt_dma(ms); in cmd_complete()
1604 cmd->SCp.Status = mr->fifo; in cmd_complete()
1607 cmd->SCp.Status); in cmd_complete()
1609 ms->msgphase = msg_in; in cmd_complete()
1612 mesh_done(ms, 1); in cmd_complete()
1615 ms->current_req = NULL; in cmd_complete()
1616 ms->phase = idle; in cmd_complete()
1617 mesh_start(ms); in cmd_complete()
1622 ++ms->phase; in cmd_complete()
1623 start_phase(ms); in cmd_complete()
1635 struct mesh_state *ms; in mesh_queue_lck() local
1637 cmd->scsi_done = done; in mesh_queue_lck()
1638 cmd->host_scribble = NULL; in mesh_queue_lck()
1640 ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_queue_lck()
1642 if (ms->request_q == NULL) in mesh_queue_lck()
1643 ms->request_q = cmd; in mesh_queue_lck()
1645 ms->request_qtail->host_scribble = (void *) cmd; in mesh_queue_lck()
1646 ms->request_qtail = cmd; in mesh_queue_lck()
1648 if (ms->phase == idle) in mesh_queue_lck()
1649 mesh_start(ms); in mesh_queue_lck()
1661 static void mesh_interrupt(struct mesh_state *ms) in DEF_SCSI_QCMD()
1663 volatile struct mesh_regs __iomem *mr = ms->mesh; in DEF_SCSI_QCMD()
1667 if (ALLOW_DEBUG(ms->conn_tgt)) in DEF_SCSI_QCMD()
1669 "phase=%d msgphase=%d\n", mr->bus_status0, in DEF_SCSI_QCMD()
1670 mr->interrupt, mr->exception, mr->error, in DEF_SCSI_QCMD()
1671 ms->phase, ms->msgphase); in DEF_SCSI_QCMD()
1673 while ((intr = in_8(&mr->interrupt)) != 0) { in DEF_SCSI_QCMD()
1674 dlog(ms, "interrupt intr/err/exc/seq=%.8x", in DEF_SCSI_QCMD()
1675 MKWORD(intr, mr->error, mr->exception, mr->sequence)); in DEF_SCSI_QCMD()
1677 handle_error(ms); in DEF_SCSI_QCMD()
1679 handle_exception(ms); in DEF_SCSI_QCMD()
1681 out_8(&mr->interrupt, INT_CMDDONE); in DEF_SCSI_QCMD()
1682 cmd_complete(ms); in DEF_SCSI_QCMD()
1688 * queue if it isn't connected yet, and for pending command, assert
1693 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_abort() local
1696 mesh_dump_regs(ms); in mesh_abort()
1697 dumplog(ms, cmd->device->id); in mesh_abort()
1698 dumpslog(ms); in mesh_abort()
1703 * Called by the midlayer with the lock held to reset the
1710 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_host_reset() local
1711 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_host_reset()
1712 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_host_reset()
1717 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_host_reset()
1719 if (ms->dma_started) in mesh_host_reset()
1720 halt_dma(ms); in mesh_host_reset()
1722 /* Reset the controller & dbdma channel */ in mesh_host_reset()
1723 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_host_reset()
1724 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_host_reset()
1725 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_host_reset()
1726 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_host_reset()
1729 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_host_reset()
1730 out_8(&mr->source_id, ms->host->this_id); in mesh_host_reset()
1731 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_host_reset()
1732 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_host_reset()
1734 /* Reset the bus */ in mesh_host_reset()
1735 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_host_reset()
1738 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_host_reset()
1741 handle_reset(ms); in mesh_host_reset()
1743 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_host_reset()
1747 static void set_mesh_power(struct mesh_state *ms, int state) in set_mesh_power() argument
1752 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1); in set_mesh_power()
1755 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0); in set_mesh_power()
1764 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); in mesh_suspend() local
1775 if (ms->phase == sleeping) in mesh_suspend()
1778 scsi_block_requests(ms->host); in mesh_suspend()
1779 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_suspend()
1780 while(ms->phase != idle) { in mesh_suspend()
1781 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_suspend()
1783 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_suspend()
1785 ms->phase = sleeping; in mesh_suspend()
1786 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_suspend()
1787 disable_irq(ms->meshintr); in mesh_suspend()
1788 set_mesh_power(ms, 0); in mesh_suspend()
1795 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); in mesh_resume() local
1798 if (ms->phase != sleeping) in mesh_resume()
1801 set_mesh_power(ms, 1); in mesh_resume()
1802 mesh_init(ms); in mesh_resume()
1803 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_resume()
1804 mesh_start(ms); in mesh_resume()
1805 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_resume()
1806 enable_irq(ms->meshintr); in mesh_resume()
1807 scsi_unblock_requests(ms->host); in mesh_resume()
1817 * So, on reboot we reset the SCSI bus.
1821 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); in mesh_shutdown() local
1826 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_shutdown()
1827 mr = ms->mesh; in mesh_shutdown()
1828 out_8(&mr->intr_mask, 0); in mesh_shutdown()
1829 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_shutdown()
1830 out_8(&mr->bus_status1, BS1_RST); in mesh_shutdown()
1833 out_8(&mr->bus_status1, 0); in mesh_shutdown()
1834 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_shutdown()
1858 struct mesh_state *ms; in mesh_probe() local
1863 switch (mdev->bus->chip->type) { in mesh_probe()
1877 return -ENODEV; in mesh_probe()
1882 return -EBUSY; in mesh_probe()
1895 mesh_host->base = macio_resource_start(mdev, 0); in mesh_probe()
1896 mesh_host->irq = macio_irq(mdev, 0); in mesh_probe()
1897 ms = (struct mesh_state *) mesh_host->hostdata; in mesh_probe()
1898 macio_set_drvdata(mdev, ms); in mesh_probe()
1899 ms->host = mesh_host; in mesh_probe()
1900 ms->mdev = mdev; in mesh_probe()
1901 ms->pdev = pdev; in mesh_probe()
1903 ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000); in mesh_probe()
1904 if (ms->mesh == NULL) { in mesh_probe()
1908 ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000); in mesh_probe()
1909 if (ms->dma == NULL) { in mesh_probe()
1911 iounmap(ms->mesh); in mesh_probe()
1915 ms->meshintr = macio_irq(mdev, 0); in mesh_probe()
1916 ms->dmaintr = macio_irq(mdev, 1); in mesh_probe()
1921 ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd); in mesh_probe()
1924 * enough or until we get some macio-specific versions in mesh_probe()
1926 dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev, in mesh_probe()
1927 ms->dma_cmd_size, &dma_cmd_bus, in mesh_probe()
1934 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space); in mesh_probe()
1935 ms->dma_cmd_space = dma_cmd_space; in mesh_probe()
1936 ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds) in mesh_probe()
1937 - (unsigned long)dma_cmd_space; in mesh_probe()
1938 ms->current_req = NULL; in mesh_probe()
1940 ms->tgts[tgt].sdtr_state = do_sdtr; in mesh_probe()
1941 ms->tgts[tgt].sync_params = ASYNC_PARAMS; in mesh_probe()
1942 ms->tgts[tgt].current_req = NULL; in mesh_probe()
1945 if ((cfp = of_get_property(mesh, "clock-frequency", NULL))) in mesh_probe()
1946 ms->clk_freq = *cfp; in mesh_probe()
1949 ms->clk_freq = 50000000; in mesh_probe()
1955 minper = 1000000000 / (ms->clk_freq / 5); /* ns */ in mesh_probe()
1960 set_mesh_power(ms, 1); in mesh_probe()
1963 mesh_init(ms); in mesh_probe()
1966 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) { in mesh_probe()
1967 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr); in mesh_probe()
1972 if (scsi_add_host(mesh_host, &mdev->ofdev.dev)) in mesh_probe()
1979 free_irq(ms->meshintr, ms); in mesh_probe()
1981 /* shutdown & reset bus in case of error or macos can be confused in mesh_probe()
1985 set_mesh_power(ms, 0); in mesh_probe()
1986 dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size, in mesh_probe()
1987 ms->dma_cmd_space, ms->dma_cmd_bus); in mesh_probe()
1989 iounmap(ms->dma); in mesh_probe()
1990 iounmap(ms->mesh); in mesh_probe()
1996 return -ENODEV; in mesh_probe()
2001 struct mesh_state *ms = (struct mesh_state *)macio_get_drvdata(mdev); in mesh_remove() local
2002 struct Scsi_Host *mesh_host = ms->host; in mesh_remove()
2006 free_irq(ms->meshintr, ms); in mesh_remove()
2008 /* Reset scsi bus */ in mesh_remove()
2012 set_mesh_power(ms, 0); in mesh_remove()
2015 iounmap(ms->mesh); in mesh_remove()
2016 iounmap(ms->dma); in mesh_remove()
2019 dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size, in mesh_remove()
2020 ms->dma_cmd_space, ms->dma_cmd_bus); in mesh_remove()