Lines Matching +full:0 +full:x02020000
32 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
33 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
34 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
35 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
36 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
37 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
38 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
39 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
40 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
41 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
42 #define PCI_DEVICE_ID_LSI_FURY 0x005f
43 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
44 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
45 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
46 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
47 #define PCI_DEVICE_ID_LSI_VENTURA 0x0014
48 #define PCI_DEVICE_ID_LSI_CRUSADER 0x0015
49 #define PCI_DEVICE_ID_LSI_HARPOON 0x0016
50 #define PCI_DEVICE_ID_LSI_TOMCAT 0x0017
51 #define PCI_DEVICE_ID_LSI_VENTURA_4PORT 0x001B
52 #define PCI_DEVICE_ID_LSI_CRUSADER_4PORT 0x001C
53 #define PCI_DEVICE_ID_LSI_AERO_10E1 0x10e1
54 #define PCI_DEVICE_ID_LSI_AERO_10E2 0x10e2
55 #define PCI_DEVICE_ID_LSI_AERO_10E5 0x10e5
56 #define PCI_DEVICE_ID_LSI_AERO_10E6 0x10e6
57 #define PCI_DEVICE_ID_LSI_AERO_10E0 0x10e0
58 #define PCI_DEVICE_ID_LSI_AERO_10E3 0x10e3
59 #define PCI_DEVICE_ID_LSI_AERO_10E4 0x10e4
60 #define PCI_DEVICE_ID_LSI_AERO_10E7 0x10e7
65 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
66 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
67 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
68 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
69 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
70 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
71 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
76 #define MEGARAID_INTRUDER_SSDID1 0x9371
77 #define MEGARAID_INTRUDER_SSDID2 0x9390
78 #define MEGARAID_INTRUDER_SSDID3 0x9370
113 #define MFI_STATE_MASK 0xF0000000
114 #define MFI_STATE_UNDEFINED 0x00000000
115 #define MFI_STATE_BB_INIT 0x10000000
116 #define MFI_STATE_FW_INIT 0x40000000
117 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
118 #define MFI_STATE_FW_INIT_2 0x70000000
119 #define MFI_STATE_DEVICE_SCAN 0x80000000
120 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
121 #define MFI_STATE_FLUSH_CACHE 0xA0000000
122 #define MFI_STATE_READY 0xB0000000
123 #define MFI_STATE_OPERATIONAL 0xC0000000
124 #define MFI_STATE_FAULT 0xF0000000
125 #define MFI_STATE_FORCE_OCR 0x00000080
126 #define MFI_STATE_DMADONE 0x00000008
127 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
128 #define MFI_RESET_REQUIRED 0x00000001
129 #define MFI_RESET_ADAPTER 0x00000002
132 #define MFI_STATE_FAULT_CODE 0x0FFF0000
133 #define MFI_STATE_FAULT_SUBCODE 0x0000FF00
145 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
146 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
147 #define DIAG_WRITE_ENABLE (0x00000080)
148 #define DIAG_RESET_ADAPTER (0x00000004)
150 #define MFI_ADP_RESET 0x00000040
151 #define MFI_INIT_ABORT 0x00000001
152 #define MFI_INIT_READY 0x00000002
153 #define MFI_INIT_MFIMODE 0x00000004
154 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
155 #define MFI_INIT_HOTPLUG 0x00000010
156 #define MFI_STOP_ADP 0x00000020
160 #define MFI_ADP_TRIGGER_SNAP_DUMP 0x00000100
161 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
166 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
167 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
168 #define MFI_FRAME_SGL32 0x0000
169 #define MFI_FRAME_SGL64 0x0002
170 #define MFI_FRAME_SENSE32 0x0000
171 #define MFI_FRAME_SENSE64 0x0004
172 #define MFI_FRAME_DIR_NONE 0x0000
173 #define MFI_FRAME_DIR_WRITE 0x0008
174 #define MFI_FRAME_DIR_READ 0x0010
175 #define MFI_FRAME_DIR_BOTH 0x0018
176 #define MFI_FRAME_IEEE 0x0020
179 #define DRV_DCMD_POLLED_MODE 0x1
180 #define DRV_DCMD_SKIP_REFIRE 0x2
185 #define MFI_CMD_STATUS_POLL_MODE 0xFF
191 MFI_CMD_INIT = 0x0,
192 MFI_CMD_LD_READ = 0x1,
193 MFI_CMD_LD_WRITE = 0x2,
194 MFI_CMD_LD_SCSI_IO = 0x3,
195 MFI_CMD_PD_SCSI_IO = 0x4,
196 MFI_CMD_DCMD = 0x5,
197 MFI_CMD_ABORT = 0x6,
198 MFI_CMD_SMP = 0x7,
199 MFI_CMD_STP = 0x8,
200 MFI_CMD_NVME = 0x9,
201 MFI_CMD_TOOLBOX = 0xa,
203 MFI_CMD_INVALID = 0xff
206 #define MR_DCMD_CTRL_GET_INFO 0x01010000
207 #define MR_DCMD_LD_GET_LIST 0x03010000
208 #define MR_DCMD_LD_LIST_QUERY 0x03010100
210 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
211 #define MR_FLUSH_CTRL_CACHE 0x01
212 #define MR_FLUSH_DISK_CACHE 0x02
214 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
215 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
216 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
218 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
219 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
220 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
221 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
223 #define MR_DCMD_CLUSTER 0x08000000
224 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
225 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
226 #define MR_DCMD_PD_LIST_QUERY 0x02010100
228 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
229 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
230 #define MR_DCMD_PD_GET_INFO 0x02020000
242 MFI_STAT_OK = 0x00,
243 MFI_STAT_INVALID_CMD = 0x01,
244 MFI_STAT_INVALID_DCMD = 0x02,
245 MFI_STAT_INVALID_PARAMETER = 0x03,
246 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
247 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
248 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
249 MFI_STAT_APP_IN_USE = 0x07,
250 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
251 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
252 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
253 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
254 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
255 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
256 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
257 MFI_STAT_FLASH_BUSY = 0x0f,
258 MFI_STAT_FLASH_ERROR = 0x10,
259 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
260 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
261 MFI_STAT_FLASH_NOT_OPEN = 0x13,
262 MFI_STAT_FLASH_NOT_STARTED = 0x14,
263 MFI_STAT_FLUSH_FAILED = 0x15,
264 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
265 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
266 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
267 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
268 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
269 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
270 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
271 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
272 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
273 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
274 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
275 MFI_STAT_MFC_HW_ERROR = 0x21,
276 MFI_STAT_NO_HW_PRESENT = 0x22,
277 MFI_STAT_NOT_FOUND = 0x23,
278 MFI_STAT_NOT_IN_ENCL = 0x24,
279 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
280 MFI_STAT_PD_TYPE_WRONG = 0x26,
281 MFI_STAT_PR_DISABLED = 0x27,
282 MFI_STAT_ROW_INDEX_INVALID = 0x28,
283 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
284 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
285 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
286 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
287 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
288 MFI_STAT_SCSI_IO_FAILED = 0x2e,
289 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
290 MFI_STAT_SHUTDOWN_FAILED = 0x30,
291 MFI_STAT_TIME_NOT_SET = 0x31,
292 MFI_STAT_WRONG_STATE = 0x32,
293 MFI_STAT_LD_OFFLINE = 0x33,
294 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
295 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
296 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
297 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
298 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
299 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
301 MFI_STAT_INVALID_STATUS = 0xFF
307 MFI_EVT_CLASS_INFO = 0,
321 UNAVAILABLE = 0,
329 MR_CRASH_BUF_TURN_OFF = 0,
342 MR_EVT_CLASS_INFO = 0,
352 MR_EVT_LOCALE_LD = 0x0001,
353 MR_EVT_LOCALE_PD = 0x0002,
354 MR_EVT_LOCALE_ENCL = 0x0004,
355 MR_EVT_LOCALE_BBU = 0x0008,
356 MR_EVT_LOCALE_SAS = 0x0010,
357 MR_EVT_LOCALE_CTRL = 0x0020,
358 MR_EVT_LOCALE_CONFIG = 0x0040,
359 MR_EVT_LOCALE_CLUSTER = 0x0080,
360 MR_EVT_LOCALE_ALL = 0xffff,
412 MR_PD_QUERY_TYPE_ALL = 0,
421 MR_LD_QUERY_TYPE_ALL = 0,
429 #define MR_EVT_CFG_CLEARED 0x0004
430 #define MR_EVT_LD_STATE_CHANGE 0x0051
431 #define MR_EVT_PD_INSERTED 0x005b
432 #define MR_EVT_PD_REMOVED 0x0070
433 #define MR_EVT_LD_CREATED 0x008a
434 #define MR_EVT_LD_DELETED 0x008b
435 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
436 #define MR_EVT_LD_OFFLINE 0x00fc
437 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
438 #define MR_EVT_CTRL_PROP_CHANGED 0x012f
441 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
442 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
443 MR_PD_STATE_HOT_SPARE = 0x02,
444 MR_PD_STATE_OFFLINE = 0x10,
445 MR_PD_STATE_FAILED = 0x11,
446 MR_PD_STATE_REBUILD = 0x14,
447 MR_PD_STATE_ONLINE = 0x18,
448 MR_PD_STATE_COPYBACK = 0x20,
449 MR_PD_STATE_SYSTEM = 0x40,
1158 char package_version[0x60];
1297 u8 reserved5[2]; /*0x7CDh */
1324 char clusterId[MEGASAS_CLUSTER_ID_SIZE]; /*0x7D4 */
1326 u8 maxVFsSupported; /*0x7E4*/
1327 u8 numVFsEnabled; /*0x7E5*/
1328 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
1329 u8 reserved; /*0x7E7*/
1454 u8 pad[0x800 - 0x7FE]; /* 0x7FE pad to 2K for expansion */
1527 #define OCR_DEBUG (1 << 0)
1531 #define SCAN_PD_CHANNEL 0x1
1532 #define SCAN_VD_CHANNEL 0x2
1539 READ_WRITE_LDIO = 0,
1546 INITIATE_OCR = 0,
1552 PROBE_CONTEXT = 0,
1557 #define IO_FRAME 0
1570 #define MEGASAS_IOCTL_CMD 0
1594 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1596 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1597 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1598 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1600 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1607 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1608 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1609 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1610 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1611 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1613 #define MFI_1068_PCSR_OFFSET 0x84
1614 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1615 #define MFI_1068_FW_READY 0xDDDD0000
1617 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1618 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1621 #define MR_RDPQ_MODE_OFFSET 0X00800000
1624 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF
1625 #define MR_MIN_MAP_SIZE 0x10000
1628 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000
1741 __le32 pad_0; /*0Ch */
1809 __le32 pad_0; /*0Ch */
1832 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1853 __le32 pad_0; /*0Ch */
1882 __le32 pad_0; /*0Ch */
1905 __le32 pad_0; /*0Ch */
1933 __le32 pad_0; /*0Ch */
1960 __le32 pad_0; /*0Ch */
1969 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1970 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1987 __le32 pad_0; /*0Ch */
1998 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1999 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
2229 UNKNOWN_DRIVE = 0,
2246 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF
2254 MR_BALANCED_PERF_MODE = 0,
2485 #define IOV_111_OFFSET 0x7CE
2519 u32 driverCounter; /* Driver heart beat counter. 0x20 */
2522 u8 pad[0x400-0x40];
2526 MEGASAS_HBA_OPERATIONAL = 0,
2532 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
2559 ((sdev->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1)
2651 FW_FAULT_OCR = 0,
2657 DCMD_SUCCESS = 0x00,
2658 DCMD_TIMEOUT = 0x01,
2659 DCMD_FAILED = 0x02,
2660 DCMD_BUSY = 0x03,
2661 DCMD_INIT = 0xff,