Lines Matching +full:0 +full:x00000001
36 * #define example_bit_field_MASK 0x03
47 * bf_set(example_bit_field, &t1, 0);
71 #define lpfc_sli_intf_valid_MASK 0x00000007
75 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
77 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
79 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
81 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
85 #define lpfc_sli_intf_if_type_MASK 0x0000000F
87 #define LPFC_SLI_INTF_IF_TYPE_0 0
92 #define lpfc_sli_intf_sli_family_MASK 0x0000000F
94 #define LPFC_SLI_INTF_FAMILY_BE2 0x0
95 #define LPFC_SLI_INTF_FAMILY_BE3 0x1
96 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
97 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
98 #define LPFC_SLI_INTF_FAMILY_G6 0xc
99 #define LPFC_SLI_INTF_FAMILY_G7 0xd
100 #define LPFC_SLI_INTF_FAMILY_G7P 0xe
102 #define lpfc_sli_intf_slirev_MASK 0x0000000F
106 #define lpfc_sli_intf_func_type_SHIFT 0
107 #define lpfc_sli_intf_func_type_MASK 0x00000001
109 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0
126 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
136 #define LPFC_MBX_ERROR_RANGE 0x4000
137 #define LPFC_BMBX_BIT1_ADDR_HI 0x2
138 #define LPFC_BMBX_BIT1_ADDR_LO 0
141 #define LPFC_RPI_ALLOC_ERROR 0xFFFF
143 #define LPFC_ENTIRE_FCF_DATABASE 0
144 #define LPFC_DFLT_FCF_INDEX 0
147 #define LPFC_VF0 0
181 #define LPFC_PCI_FUNC0 0
188 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414
189 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001
190 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002
191 #define LPFC_CTL_PDEV_CTL_DD 0x00000004
192 #define LPFC_CTL_PDEV_CTL_LC 0x00000008
193 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
194 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
195 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
196 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000
204 #define LPFC_FCP_SCHED_BY_HDWQ 0
208 #define LPFC_NS_QUERY_GID_FT 0
218 #define LPFC_DEF_IMAX 0
226 #define LPFC_MIN_CPU_MAP 0
238 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
243 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
246 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
247 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
248 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
249 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
250 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
251 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
252 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
264 #define lpfc_idx_rsrc_rdy_SHIFT 0
265 #define lpfc_idx_rsrc_rdy_MASK 0x00000001
269 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001
273 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001
277 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001
281 #define lpfc_ftr_ashdr_MASK 0x00000001
288 #define lpfc_abts_orig_SHIFT 0
289 #define lpfc_abts_orig_MASK 0x00000001
292 #define LPFC_ABTS_UNSOL_INT 0
294 #define lpfc_abts_rxid_SHIFT 0
295 #define lpfc_abts_rxid_MASK 0x0000FFFF
298 #define lpfc_abts_oxid_MASK 0x0000FFFF
301 #define lpfc_vndr_code_SHIFT 0
302 #define lpfc_vndr_code_MASK 0x000000FF
305 #define lpfc_rsn_expln_MASK 0x000000FF
308 #define lpfc_rsn_code_MASK 0x000000FF
319 #define lpfc_eqe_resource_id_MASK 0x0000FFFF
322 #define lpfc_eqe_minor_code_MASK 0x00000FFF
325 #define lpfc_eqe_major_code_MASK 0x00000007
327 #define lpfc_eqe_valid_SHIFT 0
328 #define lpfc_eqe_valid_MASK 0x00000001
339 #define lpfc_cqe_valid_MASK 0x00000001
342 #define lpfc_cqe_code_MASK 0x000000FF
347 #define CQE_STATUS_SUCCESS 0x0
348 #define CQE_STATUS_FCP_RSP_FAILURE 0x1
349 #define CQE_STATUS_REMOTE_STOP 0x2
350 #define CQE_STATUS_LOCAL_REJECT 0x3
351 #define CQE_STATUS_NPORT_RJT 0x4
352 #define CQE_STATUS_FABRIC_RJT 0x5
353 #define CQE_STATUS_NPORT_BSY 0x6
354 #define CQE_STATUS_FABRIC_BSY 0x7
355 #define CQE_STATUS_INTERMED_RSP 0x8
356 #define CQE_STATUS_LS_RJT 0x9
357 #define CQE_STATUS_CMD_REJECT 0xb
358 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc
359 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf
360 #define CQE_STATUS_DI_ERROR 0x16
363 #define LPFC_IOCB_STATUS_MASK 0xf
366 #define CQE_HW_STATUS_NO_ERR 0x0
367 #define CQE_HW_STATUS_UNDERRUN 0x1
368 #define CQE_HW_STATUS_OVERRUN 0x2
371 #define CQE_CODE_COMPL_WQE 0x1
372 #define CQE_CODE_RELEASE_WQE 0x2
373 #define CQE_CODE_RECEIVE 0x4
374 #define CQE_CODE_XRI_ABORTED 0x5
375 #define CQE_CODE_RECEIVE_V1 0x9
376 #define CQE_CODE_NVME_ERSP 0xd
380 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
382 #define WCQE_PARAM_MASK 0x1FF
388 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
391 #define lpfc_wcqe_c_status_MASK 0x000000FF
393 #define lpfc_wcqe_c_hw_status_SHIFT 0
394 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF
396 #define lpfc_wcqe_c_ersp0_SHIFT 0
397 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
401 #define lpfc_wcqe_c_cmf_cg_MASK 0x00000001
403 #define lpfc_wcqe_c_cmf_bw_SHIFT 0
404 #define lpfc_wcqe_c_cmf_bw_MASK 0x0FFFFFFF
408 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001
411 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
414 #define lpfc_wcqe_c_bg_re_MASK 0x00000001
417 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001
419 #define lpfc_wcqe_c_bg_ge_SHIFT 0
420 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001
427 #define lpfc_wcqe_c_xb_MASK 0x00000001
430 #define lpfc_wcqe_c_pv_MASK 0x00000001
433 #define lpfc_wcqe_c_priority_MASK 0x00000007
438 #define lpfc_wcqe_c_sqhead_SHIFT 0
439 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
449 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
451 #define lpfc_wcqe_r_wqe_index_SHIFT 0
452 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
466 #define lpfc_wcqe_xa_status_MASK 0x000000FF
471 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
473 #define lpfc_wcqe_xa_xri_SHIFT 0
474 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
481 #define lpfc_wcqe_xa_ia_MASK 0x00000001
483 #define CQE_XRI_ABORTED_IA_REMOTE 0
486 #define lpfc_wcqe_xa_br_MASK 0x00000001
488 #define CQE_XRI_ABORTED_BR_BA_ACC 0
491 #define lpfc_wcqe_xa_eo_MASK 0x00000001
493 #define CQE_XRI_ABORTED_EO_REMOTE 0
504 #define lpfc_rcqe_bindex_MASK 0x0000FFF
507 #define lpfc_rcqe_status_MASK 0x000000FF
509 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
510 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
511 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
512 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
514 #define lpfc_rcqe_fcf_id_v1_SHIFT 0
515 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
519 #define lpfc_rcqe_length_MASK 0x0000FFFF
522 #define lpfc_rcqe_rq_id_MASK 0x000003FF
524 #define lpfc_rcqe_fcf_id_SHIFT 0
525 #define lpfc_rcqe_fcf_id_MASK 0x0000003F
527 #define lpfc_rcqe_rq_id_v1_SHIFT 0
528 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
535 #define lpfc_rcqe_port_MASK 0x00000001
538 #define lpfc_rcqe_hdr_length_MASK 0x0000001F
544 #define lpfc_rcqe_eof_MASK 0x000000FF
546 #define FCOE_EOFn 0x41
547 #define FCOE_EOFt 0x42
548 #define FCOE_EOFni 0x49
549 #define FCOE_EOFa 0x50
550 #define lpfc_rcqe_sof_SHIFT 0
551 #define lpfc_rcqe_sof_MASK 0x000000FF
553 #define FCOE_SOFi2 0x2d
554 #define FCOE_SOFi3 0x2e
555 #define FCOE_SOFn2 0x35
556 #define FCOE_SOFn3 0x36
570 #define lpfc_bde4_last_MASK 0x00000001
572 #define lpfc_bde4_sge_offset_SHIFT 0
573 #define lpfc_bde4_sge_offset_MASK 0x000003FF
576 #define lpfc_bde4_length_SHIFT 0
577 #define lpfc_bde4_length_MASK 0x000000FF
585 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
586 #define LPFC_PORT_SEM_MASK 0xF000
587 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
588 #define LPFC_UERR_STATUS_HI 0x00A4
589 #define LPFC_UERR_STATUS_LO 0x00A0
590 #define LPFC_UE_MASK_HI 0x00AC
591 #define LPFC_UE_MASK_LO 0x00A8
593 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
594 #define LPFC_SLI_INTF 0x0058
595 #define LPFC_SLI_ASIC_VER 0x009C
597 #define LPFC_CTL_PORT_SEM_OFFSET 0x400
599 #define lpfc_port_smphr_perr_MASK 0x1
602 #define lpfc_port_smphr_sfi_MASK 0x1
605 #define lpfc_port_smphr_nip_MASK 0x1
608 #define lpfc_port_smphr_ipc_MASK 0x1
611 #define lpfc_port_smphr_scr1_MASK 0x1
614 #define lpfc_port_smphr_scr2_MASK 0x1
617 #define lpfc_port_smphr_host_scratch_MASK 0xFF
619 #define lpfc_port_smphr_port_status_SHIFT 0
620 #define lpfc_port_smphr_port_status_MASK 0xFFFF
623 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
624 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
625 #define LPFC_POST_STAGE_HOST_RDY 0x0002
626 #define LPFC_POST_STAGE_BE_RESET 0x0003
627 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
628 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
629 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
630 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
631 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
632 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
633 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400
634 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
635 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
636 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
637 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
638 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
639 #define LPFC_POST_STAGE_ARMFW_START 0x0800
640 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
641 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
642 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
643 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
644 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
645 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
646 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
647 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
648 #define LPFC_POST_STAGE_PARSE_XML 0x0B04
649 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
650 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
651 #define LPFC_POST_STAGE_RC_DONE 0x0B07
652 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
653 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
654 #define LPFC_POST_STAGE_PORT_READY 0xC000
655 #define LPFC_POST_STAGE_PORT_UE 0xF000
657 #define LPFC_CTL_PORT_STA_OFFSET 0x404
659 #define lpfc_sliport_status_err_MASK 0x1
662 #define lpfc_sliport_status_end_MASK 0x1
665 #define lpfc_sliport_status_oti_MASK 0x1
668 #define lpfc_sliport_status_dip_MASK 0x1
671 #define lpfc_sliport_status_rn_MASK 0x1
674 #define lpfc_sliport_status_rdy_MASK 0x1
678 #define LPFC_CTL_PORT_CTL_OFFSET 0x408
680 #define lpfc_sliport_ctrl_end_MASK 0x1
682 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
685 #define lpfc_sliport_ctrl_ip_MASK 0x1
689 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C
690 #define LPFC_CTL_PORT_ER2_OFFSET 0x410
692 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
694 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
696 #define lpfc_sliport_eqdelay_id_SHIFT 0
697 #define lpfc_sliport_eqdelay_id_MASK 0xfff
702 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
705 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC
707 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF
708 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
710 #define LPFC_HST_ISR0 0x0C18
711 #define LPFC_HST_ISR1 0x0C1C
712 #define LPFC_HST_ISR2 0x0C20
713 #define LPFC_HST_ISR3 0x0C24
714 #define LPFC_HST_ISR4 0x0C28
716 #define LPFC_HST_IMR0 0x0C48
717 #define LPFC_HST_IMR1 0x0C4C
718 #define LPFC_HST_IMR2 0x0C50
719 #define LPFC_HST_IMR3 0x0C54
720 #define LPFC_HST_IMR4 0x0C58
722 #define LPFC_HST_ISCR0 0x0C78
723 #define LPFC_HST_ISCR1 0x0C7C
724 #define LPFC_HST_ISCR2 0x0C80
725 #define LPFC_HST_ISCR3 0x0C84
726 #define LPFC_HST_ISCR4 0x0C88
764 * value. For UCNA ports running SLI4 and if_type 0, they reside in
770 #define LPFC_ULP0_RQ_DOORBELL 0x00A0
771 #define LPFC_ULP1_RQ_DOORBELL 0x00C0
772 #define LPFC_IF6_RQ_DOORBELL 0x0080
774 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
777 #define lpfc_rq_db_list_fm_index_MASK 0x00FF
779 #define lpfc_rq_db_list_fm_id_SHIFT 0
780 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF
783 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
785 #define lpfc_rq_db_ring_fm_id_SHIFT 0
786 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
789 #define LPFC_ULP0_WQ_DOORBELL 0x0040
790 #define LPFC_ULP1_WQ_DOORBELL 0x0060
792 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
795 #define lpfc_wq_db_list_fm_index_MASK 0x00FF
797 #define lpfc_wq_db_list_fm_id_SHIFT 0
798 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF
801 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
803 #define lpfc_wq_db_ring_fm_id_SHIFT 0
804 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
807 #define LPFC_IF6_WQ_DOORBELL 0x0040
809 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF
812 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001
815 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F
817 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0
818 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF
821 #define LPFC_EQCQ_DOORBELL 0x0120
823 #define lpfc_eqcq_doorbell_se_MASK 0x0001
825 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
828 #define lpfc_eqcq_doorbell_arm_MASK 0x0001
831 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
834 #define lpfc_eqcq_doorbell_qt_MASK 0x0001
836 #define LPFC_QUEUE_TYPE_COMPLETION 0
839 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001
841 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
842 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
845 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
847 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
848 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
851 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
856 #define LPFC_IF6_CQ_DOORBELL 0x00C0
858 #define lpfc_if6_cq_doorbell_se_MASK 0x0001
860 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0
863 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001
866 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF
868 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0
869 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF
872 #define LPFC_IF6_EQ_DOORBELL 0x0120
874 #define lpfc_if6_eq_doorbell_io_MASK 0x0001
876 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0
879 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001
882 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF
884 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0
885 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF
888 #define LPFC_BMBX 0x0160
890 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF
893 #define lpfc_bmbx_hi_MASK 0x0001
895 #define lpfc_bmbx_rdy_SHIFT 0
896 #define lpfc_bmbx_rdy_MASK 0x0001
899 #define LPFC_MQ_DOORBELL 0x0140
900 #define LPFC_IF6_MQ_DOORBELL 0x0160
902 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
904 #define lpfc_mq_doorbell_id_SHIFT 0
905 #define lpfc_mq_doorbell_id_MASK 0xFFFF
910 #define lpfc_mbox_hdr_emb_SHIFT 0
911 #define lpfc_mbox_hdr_emb_MASK 0x00000001
914 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
925 #define lpfc_mbox_hdr_opcode_SHIFT 0
926 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
929 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
932 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF
935 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
940 #define lpfc_mbox_hdr_version_SHIFT 0
941 #define lpfc_mbox_hdr_version_MASK 0x000000FF
944 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
947 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
951 #define LPFC_Q_CREATE_VERSION_0 0
952 #define LPFC_OPCODE_VERSION_0 0
957 #define lpfc_mbox_hdr_opcode_SHIFT 0
958 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF
961 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
964 #define lpfc_mbox_hdr_domain_MASK 0x000000FF
967 #define lpfc_mbox_hdr_status_SHIFT 0
968 #define lpfc_mbox_hdr_status_MASK 0x000000FF
971 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF
973 #define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2
975 #define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF
977 #define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01
978 #define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02
996 #define LPFC_EXTENT_LOCAL 0
997 #define LPFC_TIMEOUT_DEFAULT 0
998 #define LPFC_EXTENT_VERSION_DEFAULT 0
1001 #define LPFC_MBOX_SUBSYSTEM_NA 0x0
1002 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
1003 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB
1004 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
1009 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
1010 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
1013 #define LPFC_MBOX_OPCODE_NA 0x00
1014 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
1015 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
1016 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
1017 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
1018 #define LPFC_MBOX_OPCODE_NOP 0x21
1019 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
1020 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
1021 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
1022 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
1023 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
1024 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
1025 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
1026 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
1027 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
1028 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
1029 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
1030 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
1031 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
1032 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
1033 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
1034 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
1035 #define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF 0x8E
1036 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
1037 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
1038 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
1039 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
1040 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
1041 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
1042 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
1043 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
1044 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
1045 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
1046 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
1047 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
1048 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
1049 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
1050 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
1051 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
1052 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
1055 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
1056 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
1057 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
1058 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
1059 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
1060 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
1061 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
1062 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
1063 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
1064 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
1065 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
1066 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
1067 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
1068 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
1069 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
1070 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42
1073 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37
1079 #define lpfc_eq_context_size_MASK 0x00000001
1081 #define LPFC_EQE_SIZE_4 0x0
1082 #define LPFC_EQE_SIZE_16 0x1
1084 #define lpfc_eq_context_valid_MASK 0x00000001
1087 #define lpfc_eq_context_autovalid_MASK 0x00000001
1091 #define lpfc_eq_context_count_MASK 0x00000003
1093 #define LPFC_EQ_CNT_256 0x0
1094 #define LPFC_EQ_CNT_512 0x1
1095 #define LPFC_EQ_CNT_1024 0x2
1096 #define LPFC_EQ_CNT_2048 0x3
1097 #define LPFC_EQ_CNT_4096 0x4
1100 #define lpfc_eq_context_delay_multi_MASK 0x000003FF
1122 #define lpfc_post_sgl_pages_xri_SHIFT 0
1123 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1126 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1161 struct lpfc_mbx_read_object { /* Version 0 */
1166 #define lpfc_mbx_rd_object_rlen_SHIFT 0
1167 #define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF
1179 #define lpfc_mbx_rd_object_eof_MASK 0x1
1190 #define lpfc_mbx_eq_create_num_pages_SHIFT 0
1191 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1198 #define lpfc_mbx_eq_create_q_id_SHIFT 0
1199 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1223 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1224 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1245 #define lpfc_fwlog_enable_SHIFT 0
1246 #define lpfc_fwlog_enable_MASK 0x00000001
1249 #define lpfc_fwlog_loglvl_MASK 0x0000000F
1252 #define lpfc_fwlog_ra_WORD 0x00000008
1254 #define lpfc_fwlog_buffcnt_MASK 0x000000FF
1257 #define lpfc_fwlog_buffsz_MASK 0x000000FF
1260 #define lpfc_fwlog_acqe_SHIFT 0
1261 #define lpfc_fwlog_acqe_MASK 0x0000FFFF
1264 #define lpfc_fwlog_cqid_MASK 0x0000FFFF
1280 #define lpfc_cq_context_event_MASK 0x00000001
1283 #define lpfc_cq_context_valid_MASK 0x00000001
1286 #define lpfc_cq_context_count_MASK 0x00000003
1288 #define LPFC_CQ_CNT_256 0x0
1289 #define LPFC_CQ_CNT_512 0x1
1290 #define LPFC_CQ_CNT_1024 0x2
1291 #define LPFC_CQ_CNT_WORD7 0x3
1293 #define lpfc_cq_context_autovalid_MASK 0x00000001
1296 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1297 #define lpfc_cq_eq_id_MASK 0x000000FF
1299 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1300 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1312 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1314 #define lpfc_mbx_cq_create_num_pages_SHIFT 0
1315 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1322 #define lpfc_mbx_cq_create_q_id_SHIFT 0
1323 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1335 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1337 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1338 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1342 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1345 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1348 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003
1351 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1354 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001
1357 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1360 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1364 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1367 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF
1369 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1370 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1374 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1376 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1377 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1381 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1383 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1384 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1388 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1390 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1391 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1395 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1397 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1398 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1402 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1404 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1405 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1409 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1411 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1412 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1416 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1418 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1419 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1423 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1425 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1426 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1433 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1435 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1436 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1447 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1448 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1467 struct { /* Version 0 Request */
1469 #define lpfc_mbx_wq_create_num_pages_SHIFT 0
1470 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1473 #define lpfc_mbx_wq_create_dua_MASK 0x00000001
1476 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1480 #define lpfc_mbx_wq_create_bua_SHIFT 0
1481 #define lpfc_mbx_wq_create_bua_MASK 0x00000001
1484 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1488 uint32_t word0; /* Word 0 is the same as in v0 */
1490 #define lpfc_mbx_wq_create_page_size_SHIFT 0
1491 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1493 #define LPFC_WQ_PAGE_SIZE_4096 0x1
1495 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001
1498 #define lpfc_mbx_wq_create_doe_MASK 0x00000001
1501 #define lpfc_mbx_wq_create_toe_MASK 0x00000001
1504 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1506 #define LPFC_WQ_WQE_SIZE_64 0x5
1507 #define LPFC_WQ_WQE_SIZE_128 0x6
1509 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1516 #define lpfc_mbx_wq_create_q_id_SHIFT 0
1517 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1521 #define lpfc_mbx_wq_create_bar_set_SHIFT 0
1522 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1524 #define WQ_PCI_BAR_0_AND_1 0x00
1525 #define WQ_PCI_BAR_2_AND_3 0x01
1526 #define WQ_PCI_BAR_4_AND_5 0x02
1528 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1534 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001
1536 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0
1537 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF
1540 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0
1541 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F
1546 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F
1548 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0
1549 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F
1561 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1562 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1576 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1577 #define lpfc_rq_context_rqe_count_MASK 0x0000000F
1584 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1587 #define lpfc_rq_context_rqe_size_MASK 0x0000000F
1594 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1595 #define lpfc_rq_context_page_size_MASK 0x000000FF
1597 #define LPFC_RQ_PAGE_SIZE_4096 0x1
1600 #define lpfc_rq_context_data_size_MASK 0x0000FFFF
1602 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1603 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1607 #define lpfc_rq_context_cq_id_MASK 0x0000FFFF
1609 #define lpfc_rq_context_buf_size_SHIFT 0
1610 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1612 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1613 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1623 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1624 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1627 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1630 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1633 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1641 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1643 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1644 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1648 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1649 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1652 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1663 #define lpfc_mbx_rq_create_num_pages_SHIFT 0
1664 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1667 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1670 #define lpfc_mbx_rq_create_dua_MASK 0x00000001
1673 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1676 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1679 #define lpfc_mbx_rq_create_dim_MASK 0x00000001
1682 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1685 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1693 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1695 #define lpfc_mbx_rq_create_q_id_SHIFT 0
1696 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1700 #define lpfc_mbx_rq_create_bar_set_SHIFT 0
1701 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1704 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1715 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1716 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1727 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1728 #define lpfc_mq_context_cq_id_MASK 0x000003FF
1731 #define lpfc_mq_context_ring_size_MASK 0x0000000F
1733 #define LPFC_MQ_RING_SIZE_16 0x5
1734 #define LPFC_MQ_RING_SIZE_32 0x6
1735 #define LPFC_MQ_RING_SIZE_64 0x7
1736 #define LPFC_MQ_RING_SIZE_128 0x8
1739 #define lpfc_mq_context_valid_MASK 0x00000001
1750 #define lpfc_mbx_mq_create_num_pages_SHIFT 0
1751 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1758 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1759 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1770 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1771 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1774 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1778 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1780 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1781 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1782 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1783 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1784 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1786 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1789 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1792 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1794 #define LPFC_EVT_CODE_FC_NO_LINK 0x0
1795 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1796 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1797 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1798 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1799 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1800 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1802 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1809 #define lpfc_mbx_mq_create_q_id_SHIFT 0
1810 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1814 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1815 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1816 #define LPFC_ASYNC_EVENT_GROUP5 0x20
1824 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1825 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1837 #define LPFC_RSC_TYPE_FCOE_VFI 0x20
1838 #define LPFC_RSC_TYPE_FCOE_VPI 0x21
1839 #define LPFC_RSC_TYPE_FCOE_RPI 0x22
1840 #define LPFC_RSC_TYPE_FCOE_XRI 0x23
1847 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1848 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1853 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1854 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1857 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1867 #define LPFC_FC_FCOE 0x00000007
1871 #define LPFC_FCOE_INI_MODE 0x00000040
1872 #define LPFC_FCOE_TGT_MODE 0x00000080
1873 #define LPFC_DUA_MODE 0x00000800
1875 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1876 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080
1893 #define lpfc_mbx_set_beacon_port_num_SHIFT 0
1894 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1897 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1900 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1903 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1908 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF
1915 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1916 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1919 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1928 #define lpfc_mbx_set_diag_state_diag_SHIFT 0
1929 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1932 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1934 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
1937 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
1940 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
1954 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
1955 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
1957 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
1958 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
1959 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
1960 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3
1962 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
1965 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
1980 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
1983 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
1986 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0
1987 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
1990 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
1993 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
1994 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
1997 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
2028 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
2029 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
2032 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
2037 #define lpfc_mbx_rsrc_cnt_SHIFT 0
2038 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
2062 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
2063 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
2074 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
2075 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
2078 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
2089 #define lpfc_sli4_sge_offset_SHIFT 0
2090 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
2093 #define lpfc_sli4_sge_type_MASK 0x0000000F
2095 #define LPFC_SGE_TYPE_DATA 0x0
2096 #define LPFC_SGE_TYPE_DIF 0x4
2097 #define LPFC_SGE_TYPE_LSP 0x5
2098 #define LPFC_SGE_TYPE_PEDIF 0x6
2099 #define LPFC_SGE_TYPE_PESEED 0x7
2100 #define LPFC_SGE_TYPE_DISEED 0x8
2101 #define LPFC_SGE_TYPE_ENC 0x9
2102 #define LPFC_SGE_TYPE_ATM 0xA
2103 #define LPFC_SGE_TYPE_SKIP 0xC
2105 #define lpfc_sli4_sge_last_MASK 0x00000001
2132 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2133 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
2136 #define lpfc_sli4_sge_dif_af_MASK 0x00000001
2139 #define lpfc_sli4_sge_dif_na_MASK 0x00000001
2142 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001
2145 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F
2148 #define lpfc_sli4_sge_dif_last_MASK 0x00000001
2151 #define lpfc_sli4_sge_dif_apptag_SHIFT 0
2152 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
2155 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007
2158 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001
2161 #define lpfc_sli4_sge_dif_me_MASK 0x00000001
2164 #define lpfc_sli4_sge_dif_re_MASK 0x00000001
2167 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001
2170 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001
2173 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
2176 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
2186 #define lpfc_fcf_record_mac_0_SHIFT 0
2187 #define lpfc_fcf_record_mac_0_MASK 0x000000FF
2190 #define lpfc_fcf_record_mac_1_MASK 0x000000FF
2193 #define lpfc_fcf_record_mac_2_MASK 0x000000FF
2196 #define lpfc_fcf_record_mac_3_MASK 0x000000FF
2199 #define lpfc_fcf_record_mac_4_SHIFT 0
2200 #define lpfc_fcf_record_mac_4_MASK 0x000000FF
2203 #define lpfc_fcf_record_mac_5_MASK 0x000000FF
2206 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
2209 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
2214 #define lpfc_fcf_record_fab_name_0_SHIFT 0
2215 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
2218 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
2221 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2224 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2227 #define lpfc_fcf_record_fab_name_4_SHIFT 0
2228 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2231 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2234 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2237 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2240 #define lpfc_fcf_record_fc_map_0_SHIFT 0
2241 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2244 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2247 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2250 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2253 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2256 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2259 #define lpfc_fcf_record_fcf_index_SHIFT 0
2260 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2263 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2267 #define lpfc_fcf_record_switch_name_0_SHIFT 0
2268 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2271 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2274 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2277 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2280 #define lpfc_fcf_record_switch_name_4_SHIFT 0
2281 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2284 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2287 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2290 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2299 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2300 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2308 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2309 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2316 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2317 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2325 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2326 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2329 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2336 #define lpfc_mbx_redisc_fcf_count_SHIFT 0
2337 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2341 #define lpfc_mbx_redisc_fcf_index_SHIFT 0
2342 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2347 #define STATUS_SUCCESS 0x0
2348 #define STATUS_FAILED 0x1
2349 #define STATUS_ILLEGAL_REQUEST 0x2
2350 #define STATUS_ILLEGAL_FIELD 0x3
2351 #define STATUS_INSUFFICIENT_BUFFER 0x4
2352 #define STATUS_UNAUTHORIZED_REQUEST 0x5
2353 #define STATUS_FLASHROM_SAVE_FAILED 0x17
2354 #define STATUS_FLASHROM_RESTORE_FAILED 0x18
2355 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2356 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2357 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2358 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2359 #define STATUS_ASSERT_FAILED 0x1e
2360 #define STATUS_INVALID_SESSION 0x1f
2361 #define STATUS_INVALID_CONNECTION 0x20
2362 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2363 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2364 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2365 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2366 #define STATUS_FLASHROM_READ_FAILED 0x27
2367 #define STATUS_POLL_IOCTL_TIMEOUT 0x28
2368 #define STATUS_ERROR_ACITMAIN 0x2a
2369 #define STATUS_REBOOT_REQUIRED 0x2c
2370 #define STATUS_FCF_IN_USE 0x3a
2371 #define STATUS_FCF_TABLE_EMPTY 0x43
2377 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2378 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB
2379 #define ADD_STATUS_INVALID_REQUEST 0x4B
2380 #define ADD_STATUS_INVALID_OBJECT_NAME 0xA0
2381 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58
2390 #define lpfc_init_vfi_vr_MASK 0x00000001
2393 #define lpfc_init_vfi_vt_MASK 0x00000001
2396 #define lpfc_init_vfi_vf_MASK 0x00000001
2399 #define lpfc_init_vfi_vp_MASK 0x00000001
2401 #define lpfc_init_vfi_vfi_SHIFT 0
2402 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2406 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2408 #define lpfc_init_vfi_fcfi_SHIFT 0
2409 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2413 #define lpfc_init_vfi_pri_MASK 0x00000007
2416 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2420 #define lpfc_init_vfi_hop_count_MASK 0x000000FF
2423 #define MBX_VFI_IN_USE 0x9F02
2429 #define lpfc_reg_vfi_upd_MASK 0x00000001
2432 #define lpfc_reg_vfi_vp_MASK 0x00000001
2434 #define lpfc_reg_vfi_vfi_SHIFT 0
2435 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2439 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2441 #define lpfc_reg_vfi_fcfi_SHIFT 0
2442 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2449 #define lpfc_reg_vfi_nport_id_SHIFT 0
2450 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2453 #define lpfc_reg_vfi_bbcr_MASK 0x00000001
2456 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2463 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2465 #define lpfc_init_vpi_vpi_SHIFT 0
2466 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2473 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2474 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2478 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2479 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2482 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2485 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2488 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2491 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2495 #define lpfc_mbx_read_vpi_vpi_SHIFT 0
2496 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2499 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2500 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2503 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2506 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2509 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2512 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2513 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2516 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2519 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2522 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2529 #define lpfc_unreg_vfi_vfi_SHIFT 0
2530 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2536 #define lpfc_resume_rpi_index_SHIFT 0
2537 #define lpfc_resume_rpi_index_MASK 0x0000FFFF
2540 #define lpfc_resume_rpi_ii_MASK 0x00000003
2542 #define RESUME_INDEX_RPI 0
2549 #define REG_FCF_INVALID_QID 0xFFFF
2552 #define lpfc_reg_fcfi_info_index_SHIFT 0
2553 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2556 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2559 #define lpfc_reg_fcfi_rq_id1_SHIFT 0
2560 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2563 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2566 #define lpfc_reg_fcfi_rq_id3_SHIFT 0
2567 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2570 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2574 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2577 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2580 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2582 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2583 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2587 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2590 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2593 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2595 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2596 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2600 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2603 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2606 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2608 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2609 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2613 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2616 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2619 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2621 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2622 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2626 #define lpfc_reg_fcfi_mam_MASK 0x00000003
2628 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2632 #define lpfc_reg_fcfi_vv_MASK 0x00000001
2634 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2635 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2641 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2642 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2645 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2648 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2649 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2652 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2655 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2656 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2659 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2663 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2666 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2669 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2671 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2672 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2676 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2679 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2682 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2684 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2685 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2689 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2692 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2695 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2697 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2698 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2702 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2705 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2708 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2710 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2711 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2715 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2718 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2721 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2724 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2727 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2730 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2733 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2736 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2739 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2742 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2745 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2748 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2751 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2754 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2757 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2760 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2763 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2766 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2769 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2771 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2772 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2776 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2779 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2781 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2782 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2796 #define lpfc_unreg_fcfi_SHIFT 0
2797 #define lpfc_unreg_fcfi_MASK 0x0000FFFF
2804 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2807 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2810 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2812 #define LPFC_PREDCBX_CEE_MODE 0
2815 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2818 #define LPFC_G7_ASIC_1 0xd
2823 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2824 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2827 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2830 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2833 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2842 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2843 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2854 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2857 #define lpfc_mbx_rd_conf_wcs_MASK 0x00000001
2860 #define lpfc_mbx_rd_conf_acs_MASK 0x00000001
2863 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2864 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2867 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2869 #define LPFC_LNK_TYPE_GE 0
2872 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2875 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F
2878 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003
2881 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001
2884 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001
2887 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2891 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2892 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2896 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2897 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2900 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2904 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2905 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2908 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2911 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2914 #define lpfc_mbx_rd_conf_lmt_SHIFT 0
2915 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2920 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0
2921 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
2924 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
2927 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
2928 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
2931 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
2934 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
2935 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
2938 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
2941 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
2942 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
2945 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
2949 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
2952 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0
2953 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
2956 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
2959 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0
2960 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
2963 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
2969 #define lpfc_mbx_rq_ftr_qry_SHIFT 0
2970 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
2973 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
2974 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
2977 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
2980 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
2983 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
2986 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
2989 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
2992 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
2995 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
2998 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
3001 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001
3004 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
3007 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001
3010 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
3011 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
3014 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
3017 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
3020 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
3023 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
3026 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
3029 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
3032 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
3035 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001
3038 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
3041 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001
3047 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0
3048 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
3051 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
3054 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
3055 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
3058 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
3061 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0
3062 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
3069 #define DMP_PAGE_A0 0xa0
3070 #define DMP_PAGE_A2 0xa2
3081 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
3082 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
3083 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
3084 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
3085 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
3086 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
3087 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
3088 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
3089 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
3090 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
3091 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
3092 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3093 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3094 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
3095 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3096 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
3100 #define SSF_IDENTIFIER 0
3141 #define SSF_TEMP_HIGH_ALARM 0
3266 #define cfg_prot_type_SHIFT 0
3267 #define cfg_prot_type_MASK 0x000000FF
3270 #define cfg_ft_SHIFT 0
3271 #define cfg_ft_MASK 0x00000001
3274 #define cfg_sli_rev_MASK 0x0000000f
3277 #define cfg_sli_family_MASK 0x0000000f
3280 #define cfg_if_type_MASK 0x0000000f
3283 #define cfg_sli_hint_1_MASK 0x000000ff
3286 #define cfg_sli_hint_2_MASK 0x0000001f
3290 #define cfg_eqav_MASK 0x00000001
3295 #define cfg_cqv_MASK 0x00000003
3298 #define cfg_cqpsize_MASK 0x000000ff
3301 #define cfg_cqav_MASK 0x00000001
3306 #define cfg_mqv_MASK 0x00000003
3310 #define cfg_wqpcnt_SHIFT 0
3311 #define cfg_wqpcnt_MASK 0x0000000f
3314 #define cfg_wqsize_MASK 0x0000000f
3317 #define cfg_wqv_MASK 0x00000003
3320 #define cfg_wqpsize_MASK 0x000000ff
3325 #define cfg_rqv_MASK 0x00000003
3329 #define cfg_rq_db_window_MASK 0x0000000f
3332 #define cfg_fcoe_SHIFT 0
3333 #define cfg_fcoe_MASK 0x00000001
3336 #define cfg_ext_MASK 0x00000001
3339 #define cfg_hdrr_MASK 0x00000001
3342 #define cfg_phwq_MASK 0x00000001
3345 #define cfg_oas_MASK 0x00000001
3348 #define cfg_loopbk_scope_MASK 0x0000000f
3352 #define cfg_sgl_page_cnt_SHIFT 0
3353 #define cfg_sgl_page_cnt_MASK 0x0000000f
3356 #define cfg_sgl_page_size_MASK 0x000000ff
3359 #define cfg_sgl_pp_align_MASK 0x000000ff
3366 #define cfg_ext_embed_cb_SHIFT 0
3367 #define cfg_ext_embed_cb_MASK 0x00000001
3370 #define cfg_mds_diags_MASK 0x00000001
3373 #define cfg_nvme_MASK 0x00000001
3376 #define cfg_xib_MASK 0x00000001
3379 #define cfg_xpsgl_MASK 0x00000001
3382 #define cfg_eqdr_MASK 0x00000001
3385 #define cfg_nosr_MASK 0x00000001
3388 #define cfg_bv1s_MASK 0x00000001
3392 #define cfg_nsler_MASK 0x00000001
3395 #define cfg_pvl_MASK 0x00000001
3399 #define cfg_pbde_MASK 0x00000001
3403 #define cfg_max_tow_xri_SHIFT 0
3404 #define cfg_max_tow_xri_MASK 0x0000ffff
3408 #define cfg_mi_ver_SHIFT 0
3409 #define cfg_mi_ver_MASK 0x0000ffff
3412 #define cfg_cmf_MASK 0x000000ff
3419 #define cfg_frag_field_offset_SHIFT 0
3420 #define cfg_frag_field_offset_MASK 0x0000ffff
3424 #define cfg_frag_field_size_MASK 0x0000ffff
3428 #define cfg_sgl_field_offset_SHIFT 0
3429 #define cfg_sgl_field_offset_MASK 0x0000ffff
3433 #define cfg_sgl_field_size_MASK 0x0000ffff
3441 #define LPFC_SET_UE_RECOVERY 0x10
3442 #define LPFC_SET_MDS_DIAGS 0x12
3443 #define LPFC_SET_CGN_SIGNAL 0x1f
3444 #define LPFC_SET_DUAL_DUMP 0x1e
3445 #define LPFC_SET_ENABLE_MI 0x21
3446 #define LPFC_SET_ENABLE_CMF 0x24
3452 #define lpfc_mbx_set_feature_UER_SHIFT 0
3453 #define lpfc_mbx_set_feature_UER_MASK 0x00000001
3456 #define lpfc_mbx_set_feature_mds_MASK 0x00000001
3459 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3461 #define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0
3462 #define lpfc_mbx_set_feature_CGN_warn_freq_MASK 0x0000ffff
3464 #define lpfc_mbx_set_feature_dd_SHIFT 0
3465 #define lpfc_mbx_set_feature_dd_MASK 0x00000001
3468 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001
3470 #define LPFC_DISABLE_DUAL_DUMP 0
3473 #define lpfc_mbx_set_feature_cmf_SHIFT 0
3474 #define lpfc_mbx_set_feature_cmf_MASK 0x00000001
3476 #define lpfc_mbx_set_feature_mi_SHIFT 0
3477 #define lpfc_mbx_set_feature_mi_MASK 0x0000ffff
3480 #define lpfc_mbx_set_feature_milunq_MASK 0x0000ffff
3483 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3484 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3487 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3489 #define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0
3490 #define lpfc_mbx_set_feature_CGN_alarm_freq_MASK 0x0000ffff
3493 #define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0
3494 #define lpfc_mbx_set_feature_CGN_acqe_freq_MASK 0x000000ff
3499 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3500 #define LPFC_SET_HOST_DATE_TIME 0x4
3506 #define lpfc_mbx_set_host_month_MASK 0xFF
3509 #define lpfc_mbx_set_host_day_MASK 0xFF
3511 #define lpfc_mbx_set_host_year_SHIFT 0
3512 #define lpfc_mbx_set_host_year_MASK 0xFF
3516 #define lpfc_mbx_set_host_hour_MASK 0xFF
3519 #define lpfc_mbx_set_host_min_MASK 0xFF
3521 #define lpfc_mbx_set_host_sec_SHIFT 0
3522 #define lpfc_mbx_set_host_sec_MASK 0xFF
3540 #define lpfc_mbx_set_trunk_mode_SHIFT 0
3541 #define lpfc_mbx_set_trunk_mode_MASK 0xFF
3555 #define lpfc_mbx_reg_cgn_buf_type_SHIFT 0
3556 #define lpfc_mbx_reg_cgn_buf_type_MASK 0xFF
3559 #define lpfc_mbx_reg_cgn_buf_cnt_MASK 0xFF
3573 #define lpfc_rsrc_desc_pcie_type_SHIFT 0
3574 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3576 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3578 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3581 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3582 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3586 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3587 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3590 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3593 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3596 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3597 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3603 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3604 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3606 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3608 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3610 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3614 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3615 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3618 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3621 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3622 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3625 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3628 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3629 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3632 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3635 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3636 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3639 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3642 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3643 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3646 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3656 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3657 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3660 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3663 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3666 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3669 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3687 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3688 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3689 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3701 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3702 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3703 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3707 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3708 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3711 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3725 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0
3726 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff
3729 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff
3732 #define lpfc_cntl_attr_flash_id_MASK 0x000000ff
3749 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0
3750 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff
3753 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3756 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff
3760 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0
3761 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff
3764 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff
3767 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3770 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0
3771 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff
3774 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff
3777 #define lpfc_cntl_attr_cache_valid_SHIFT 0
3778 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff
3781 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3784 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff
3787 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3790 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3797 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3798 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3801 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3804 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3805 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3808 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3811 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3812 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3815 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3818 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3821 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff
3825 #define lpfc_cntl_attr_num_netfil_SHIFT 0
3826 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff
3841 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3842 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3847 #define lpfc_mbx_get_port_name_name0_SHIFT 0
3848 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3851 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3854 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3857 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3859 #define LPFC_LINK_NUMBER_0 0
3868 #define MB_CQE_STATUS_SUCCESS 0x0
3869 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3870 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3871 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3872 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3873 #define MB_CQE_STATUS_DMA_FAILED 0x5
3883 #define lpfc_wr_object_eof_MASK 0x00000001
3886 #define lpfc_wr_object_eas_MASK 0x00000001
3888 #define lpfc_wr_object_write_length_SHIFT 0
3889 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3899 #define lpfc_wr_object_change_status_SHIFT 0
3900 #define lpfc_wr_object_change_status_MASK 0x000000FF
3902 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00
3903 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01
3904 #define LPFC_CHANGE_STATUS_FW_RESET 0x02
3905 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04
3906 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05
3908 #define lpfc_wr_object_csf_MASK 0x00000001
3918 #define lpfc_mqe_status_MASK 0x0000FFFF
3921 #define lpfc_mqe_command_MASK 0x000000FF
3986 #define lpfc_mcqe_status_SHIFT 0
3987 #define lpfc_mcqe_status_MASK 0x0000FFFF
3990 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF
3996 #define lpfc_trailer_valid_MASK 0x00000001
3999 #define lpfc_trailer_async_MASK 0x00000001
4002 #define lpfc_trailer_hpi_MASK 0x00000001
4005 #define lpfc_trailer_completed_MASK 0x00000001
4008 #define lpfc_trailer_consumed_MASK 0x00000001
4011 #define lpfc_trailer_type_MASK 0x000000FF
4014 #define lpfc_trailer_code_MASK 0x000000FF
4016 #define LPFC_TRAILER_CODE_LINK 0x1
4017 #define LPFC_TRAILER_CODE_FCOE 0x2
4018 #define LPFC_TRAILER_CODE_DCBX 0x3
4019 #define LPFC_TRAILER_CODE_GRP5 0x5
4020 #define LPFC_TRAILER_CODE_FC 0x10
4021 #define LPFC_TRAILER_CODE_SLI 0x11
4022 #define LPFC_TRAILER_CODE_CMSTAT 0x13
4028 #define lpfc_acqe_link_speed_MASK 0x000000FF
4030 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
4031 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
4032 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
4033 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
4034 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
4035 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
4036 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
4037 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
4038 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
4040 #define lpfc_acqe_link_duplex_MASK 0x000000FF
4042 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
4043 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
4044 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
4046 #define lpfc_acqe_link_status_MASK 0x000000FF
4048 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
4049 #define LPFC_ASYNC_LINK_STATUS_UP 0x1
4050 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
4051 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
4053 #define lpfc_acqe_link_type_MASK 0x00000003
4055 #define lpfc_acqe_link_number_SHIFT 0
4056 #define lpfc_acqe_link_number_MASK 0x0000003F
4059 #define lpfc_acqe_link_fault_SHIFT 0
4060 #define lpfc_acqe_link_fault_MASK 0x000000FF
4062 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0
4063 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
4064 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
4065 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3
4067 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
4071 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
4072 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
4078 #define lpfc_acqe_fip_fcf_count_SHIFT 0
4079 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
4082 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
4086 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
4087 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
4088 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
4089 #define LPFC_FIP_EVENT_TYPE_CVL 0x4
4090 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
4103 #define lpfc_acqe_grp5_type_MASK 0x00000003
4105 #define lpfc_acqe_grp5_number_SHIFT 0
4106 #define lpfc_acqe_grp5_number_MASK 0x0000003F
4110 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
4121 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF
4123 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0
4124 #define LPFC_FC_LA_SPEED_1G 0x1
4125 #define LPFC_FC_LA_SPEED_2G 0x2
4126 #define LPFC_FC_LA_SPEED_4G 0x4
4127 #define LPFC_FC_LA_SPEED_8G 0x8
4128 #define LPFC_FC_LA_SPEED_10G 0xA
4129 #define LPFC_FC_LA_SPEED_16G 0x10
4130 #define LPFC_FC_LA_SPEED_32G 0x20
4131 #define LPFC_FC_LA_SPEED_64G 0x21
4132 #define LPFC_FC_LA_SPEED_128G 0x22
4133 #define LPFC_FC_LA_SPEED_256G 0x23
4135 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF
4137 #define LPFC_FC_LA_TOP_UNKOWN 0x0
4138 #define LPFC_FC_LA_TOP_P2P 0x1
4139 #define LPFC_FC_LA_TOP_FCAL 0x2
4140 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
4141 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
4143 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
4145 #define LPFC_FC_LA_TYPE_LINK_UP 0x1
4146 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
4147 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
4148 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
4149 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
4150 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
4151 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7
4153 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003
4155 #define LPFC_LINK_TYPE_ETHERNET 0x0
4156 #define LPFC_LINK_TYPE_FC 0x1
4157 #define lpfc_acqe_fc_la_port_number_SHIFT 0
4158 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
4161 /* Attention Type is 0x07 (Trunking Event) word0 */
4163 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001
4166 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001
4169 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001
4172 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001
4175 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001
4178 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001
4181 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001
4184 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001
4188 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
4190 #define lpfc_acqe_fc_la_fault_SHIFT 0
4191 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF
4193 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0
4194 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F
4197 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F
4199 #define LPFC_FC_LA_FAULT_NONE 0x0
4200 #define LPFC_FC_LA_FAULT_LOCAL 0x1
4201 #define LPFC_FC_LA_FAULT_REMOTE 0x2
4204 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
4205 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
4211 #define lpfc_sli_misconfigured_port0_state_SHIFT 0
4212 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
4215 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
4218 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
4221 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
4224 #define lpfc_sli_misconfigured_port0_op_SHIFT 0
4225 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
4228 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
4231 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
4234 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
4237 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
4240 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
4243 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
4246 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
4249 #define LPFC_SLI_EVENT_STATUS_VALID 0x00
4250 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
4251 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
4252 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
4253 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
4254 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
4259 #define lpfc_warn_acqe_SHIFT 0
4260 #define lpfc_warn_acqe_MASK 0x7FFFFFFF
4263 #define lpfc_imm_acqe_MASK 0x1
4275 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
4276 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
4277 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
4278 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
4279 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
4280 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
4281 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
4282 #define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG 0xE
4283 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF
4284 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10
4285 #define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL 0x11
4302 #define NO_XRI 0xffff
4306 #define wqe_xri_tag_SHIFT 0
4307 #define wqe_xri_tag_MASK 0x0000FFFF
4310 #define wqe_ctxt_tag_MASK 0x0000FFFF
4313 #define wqe_dif_SHIFT 0
4314 #define wqe_dif_MASK 0x00000003
4320 #define wqe_ct_MASK 0x00000003
4323 #define wqe_status_MASK 0x0000000f
4326 #define wqe_cmnd_MASK 0x000000ff
4329 #define wqe_class_MASK 0x00000007
4332 #define wqe_ar_MASK 0x00000001
4338 #define wqe_pu_MASK 0x00000003
4341 #define wqe_erp_MASK 0x00000001
4347 #define wqe_lnk_MASK 0x00000001
4350 #define wqe_tmo_MASK 0x000000ff
4354 #define wqe_reqtag_SHIFT 0
4355 #define wqe_reqtag_MASK 0x0000FFFF
4358 #define wqe_temp_rpi_MASK 0x0000FFFF
4361 #define wqe_rcvoxid_MASK 0x0000FFFF
4364 #define wqe_sof_MASK 0x000000FF
4367 #define wqe_eof_MASK 0x000000FF
4370 #define wqe_ebde_cnt_SHIFT 0
4371 #define wqe_ebde_cnt_MASK 0x0000000f
4374 #define wqe_xchg_MASK 0x00000001
4376 #define LPFC_SCSI_XCHG 0x0
4377 #define LPFC_NVME_XCHG 0x1
4379 #define wqe_appid_MASK 0x00000001
4382 #define wqe_oas_MASK 0x00000001
4385 #define wqe_lenloc_MASK 0x00000003
4387 #define LPFC_WQE_LENLOC_NONE 0
4392 #define wqe_qosd_MASK 0x00000001
4395 #define wqe_xbl_MASK 0x00000001
4398 #define wqe_iod_MASK 0x00000001
4400 #define LPFC_WQE_IOD_NONE 0
4401 #define LPFC_WQE_IOD_WRITE 0
4404 #define wqe_dbde_MASK 0x00000001
4407 #define wqe_wqes_MASK 0x00000001
4411 #define wqe_wqid_MASK 0x00007fff
4414 #define wqe_pri_MASK 0x00000007
4417 #define wqe_pv_MASK 0x00000001
4420 #define wqe_xc_MASK 0x00000001
4423 #define wqe_sr_MASK 0x00000001
4426 #define wqe_ccpe_MASK 0x00000001
4429 #define wqe_ccp_MASK 0x000000ff
4432 #define wqe_cmd_type_SHIFT 0
4433 #define wqe_cmd_type_MASK 0x0000000f
4436 #define wqe_els_id_MASK 0x00000003
4441 #define LPFC_ELS_ID_DEFAULT 0
4443 #define wqe_irsp_MASK 0x00000001
4446 #define wqe_pbde_MASK 0x00000001
4449 #define wqe_sup_MASK 0x00000001
4452 #define wqe_wqec_MASK 0x00000001
4455 #define wqe_irsplen_MASK 0x0000000f
4458 #define wqe_cqid_MASK 0x0000ffff
4460 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4465 #define wqe_els_did_SHIFT 0
4466 #define wqe_els_did_MASK 0x00FFFFFF
4469 #define wqe_xmit_bls_pt_MASK 0x00000003
4472 #define wqe_xmit_bls_ar_MASK 0x00000001
4475 #define wqe_xmit_bls_xo_MASK 0x00000001
4492 #define els_req64_sid_SHIFT 0
4493 #define els_req64_sid_MASK 0x00FFFFFF
4496 #define els_req64_sp_MASK 0x00000001
4499 #define els_req64_vf_MASK 0x00000001
4505 #define els_req64_vfid_MASK 0x00000FFF
4508 #define els_req64_pri_MASK 0x00000007
4512 #define els_req64_hopcnt_MASK 0x000000ff
4522 #define els_rsp64_sid_SHIFT 0
4523 #define els_rsp64_sid_MASK 0x00FFFFFF
4526 #define els_rsp64_sp_MASK 0x00000001
4531 #define wqe_rsp_temp_rpi_SHIFT 0
4532 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4541 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4544 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4547 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4548 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4551 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4554 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4557 #define xmit_bls_rsp64_rxid_SHIFT 0
4558 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4561 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4564 #define xmit_bls_rsp64_seqcnthi_SHIFT 0
4565 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4568 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4575 #define xmit_bls_rsp64_temprpi_SHIFT 0
4576 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4584 #define wqe_si_MASK 0x000000001
4587 #define wqe_la_MASK 0x000000001
4590 #define wqe_xo_MASK 0x000000001
4593 #define wqe_ls_MASK 0x000000001
4596 #define wqe_dfctl_MASK 0x0000000ff
4599 #define wqe_type_MASK 0x0000000ff
4602 #define wqe_rctl_MASK 0x0000000ff
4642 #define prli_acc_rsp_code_MASK 0x0000000f
4645 #define prli_estabImagePair_MASK 0x00000001
4648 #define prli_type_code_ext_MASK 0x000000ff
4651 #define prli_type_code_MASK 0x000000ff
4657 #define prli_fba_SHIFT 0
4658 #define prli_fba_MASK 0x00000001
4661 #define prli_disc_MASK 0x00000001
4664 #define prli_tgt_MASK 0x00000001
4667 #define prli_init_MASK 0x00000001
4670 #define prli_conf_MASK 0x00000001
4673 #define prli_nsler_MASK 0x00000001
4676 #define prli_fb_sz_SHIFT 0
4677 #define prli_fb_sz_MASK 0x0000ffff
4683 uint32_t rsrvd[5]; /* words 0-4 */
4696 #define cmf_sync_interval_SHIFT 0
4697 #define cmf_sync_interval_MASK 0x00000ffff
4700 #define cmf_sync_afpin_MASK 0x000000001
4703 #define cmf_sync_asig_MASK 0x000000001
4706 #define cmf_sync_op_MASK 0x00000000f
4709 #define cmf_sync_ver_MASK 0x0000000ff
4714 #define cmf_sync_wsigmax_SHIFT 0
4715 #define cmf_sync_wsigmax_MASK 0x00000ffff
4718 #define cmf_sync_wsigcnt_MASK 0x00000ffff
4723 #define cmf_sync_cmnd_MASK 0x0000000ff
4727 #define cmf_sync_reqtag_SHIFT 0
4728 #define cmf_sync_reqtag_MASK 0x00000ffff
4731 #define cmf_sync_wfpinmax_MASK 0x0000000ff
4734 #define cmf_sync_wfpincnt_MASK 0x0000000ff
4738 #define cmf_sync_qosd_MASK 0x00000001
4741 #define cmf_sync_cmd_type_SHIFT 0
4742 #define cmf_sync_cmd_type_MASK 0x0000000f
4745 #define cmf_sync_wqec_MASK 0x00000001
4748 #define cmf_sync_cqid_MASK 0x0000ffff
4759 #define abort_cmd_ia_SHIFT 0
4760 #define abort_cmd_ia_MASK 0x000000001
4763 #define abort_cmd_criteria_MASK 0x0000000ff
4775 #define cmd_buff_len_MASK 0x00000ffff
4777 #define payload_offset_len_SHIFT 0
4778 #define payload_offset_len_MASK 0x0000ffff
4791 #define cmd_buff_len_MASK 0x00000ffff
4793 #define payload_offset_len_SHIFT 0
4794 #define payload_offset_len_MASK 0x0000ffff
4804 struct ulp_bde64 bde; /* words 0-2 */
4807 #define cmd_buff_len_MASK 0x00000ffff
4809 #define payload_offset_len_SHIFT 0
4810 #define payload_offset_len_MASK 0x0000ffff
4847 #define CMD_SEND_FRAME 0xE1
4850 struct ulp_bde64 bde; /* words 0-2 */
4920 #define MAGIC_NUMBER_G6 0xFEAA0003
4921 #define MAGIC_NUMBER_G7 0xFEAA0005
4922 #define MAGIC_NUMBER_G7P 0xFEAA0020
4929 #define lpfc_grp_hdr_file_type_MASK 0x000000FF
4932 #define lpfc_grp_hdr_id_MASK 0x000000FF
4940 #define FCP_COMMAND 0x0
4941 #define NVME_READ_CMD 0x0
4942 #define FCP_COMMAND_DATA_OUT 0x1
4943 #define NVME_WRITE_CMD 0x1
4944 #define COMMAND_DATA_IN 0x0
4945 #define COMMAND_DATA_OUT 0x1
4946 #define FCP_COMMAND_TRECEIVE 0x2
4947 #define FCP_COMMAND_TRSP 0x3
4948 #define FCP_COMMAND_TSEND 0x7
4949 #define OTHER_COMMAND 0x8
4950 #define CMF_SYNC_COMMAND 0xA
4951 #define ELS_COMMAND_NON_FIP 0xC
4952 #define ELS_COMMAND_FIP 0xD
4954 #define LPFC_NVME_EMBED_CMD 0x0
4955 #define LPFC_NVME_EMBED_WRITE 0x1
4956 #define LPFC_NVME_EMBED_READ 0x2
4959 #define CMD_ABORT_XRI_WQE 0x0F
4960 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4961 #define CMD_XMIT_BCAST64_WQE 0x84
4962 #define CMD_ELS_REQUEST64_WQE 0x8A
4963 #define CMD_XMIT_ELS_RSP64_WQE 0x95
4964 #define CMD_XMIT_BLS_RSP64_WQE 0x97
4965 #define CMD_FCP_IWRITE64_WQE 0x98
4966 #define CMD_FCP_IREAD64_WQE 0x9A
4967 #define CMD_FCP_ICMND64_WQE 0x9C
4968 #define CMD_FCP_TSEND64_WQE 0x9F
4969 #define CMD_FCP_TRECEIVE64_WQE 0xA1
4970 #define CMD_FCP_TRSP64_WQE 0xA3
4971 #define CMD_GEN_REQUEST64_WQE 0xC2
4972 #define CMD_CMF_SYNC_WQE 0xE8
4974 #define CMD_WQE_MASK 0xff
4986 #define ELS_DTAG_LNK_FAULT_CAP 0x0001000D
4989 #define ELS_DTAG_CG_SIGNAL_CAP 0x0001000F