Lines Matching refs:mem_ptr
2054 (unsigned long)ha->mem_ptr); in ips_host_info()
2254 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2258 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_get_bios_version()
2261 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2265 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_get_bios_version()
2269 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2273 major = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2276 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2279 minor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
2282 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); in ips_get_bios_version()
2285 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_get_bios_version()
4262 if (ha->mem_ptr) { in ips_free()
4265 ha->mem_ptr = NULL; in ips_free()
4508 isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isinit_copperhead_memio()
4509 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); in ips_isinit_copperhead_memio()
4537 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_isinit_morpheus()
4538 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isinit_morpheus()
4667 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_enable_int_copperhead_memio()
4668 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ in ips_enable_int_copperhead_memio()
4686 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4688 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_enable_int_morpheus()
4689 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ in ips_enable_int_morpheus()
4806 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4818 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4819 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4832 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4844 readb(ha->mem_ptr + IPS_REG_ISPR); in ips_init_copperhead_memio()
4845 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4849 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); in ips_init_copperhead_memio()
4863 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); in ips_init_copperhead_memio()
4866 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); in ips_init_copperhead_memio()
4870 writel(0, ha->mem_ptr + IPS_REG_NDAE); in ips_init_copperhead_memio()
4873 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); in ips_init_copperhead_memio()
4901 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4918 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4926 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4929 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); in ips_init_morpheus()
4946 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4957 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4974 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_morpheus()
4978 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); in ips_init_morpheus()
4981 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
4983 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); in ips_init_morpheus()
5065 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5070 writeb(0, ha->mem_ptr + IPS_REG_SCPR); in ips_reset_copperhead_memio()
5111 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); in ips_reset_morpheus()
5182 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); in ips_statinit_memio()
5184 ha->mem_ptr + IPS_REG_SQER); in ips_statinit_memio()
5185 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); in ips_statinit_memio()
5186 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); in ips_statinit_memio()
5241 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); in ips_statupd_copperhead_memio()
5262 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); in ips_statupd_morpheus()
5352 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { in ips_issue_copperhead_memio()
5368 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); in ips_issue_copperhead_memio()
5369 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); in ips_issue_copperhead_memio()
5433 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); in ips_issue_i2o_memio()
5487 Isr = readb(ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5498 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); in ips_isintr_copperhead_memio()
5520 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); in ips_isintr_morpheus()
6140 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6144 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6149 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6154 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6159 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6167 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6171 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6185 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6193 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_erase_bios_memio()
6197 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6221 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6226 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_erase_bios_memio()
6346 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6350 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6354 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6362 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6366 status = readb(ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6377 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6381 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6391 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6395 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6404 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_program_bios_memio()
6408 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); in ips_program_bios_memio()
6482 writel(0, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6486 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) in ips_verify_bios_memio()
6489 writel(1, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6492 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) in ips_verify_bios_memio()
6498 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); in ips_verify_bios_memio()
6503 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); in ips_verify_bios_memio()
6847 char __iomem *mem_ptr; in ips_init_phase1() local
6891 mem_ptr = ioremap_ptr + offs; in ips_init_phase1()
6894 mem_ptr = NULL; in ips_init_phase1()
6914 ha->mem_ptr = mem_ptr; in ips_init_phase1()
7016 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); in ips_init_phase1()