67 #define QDSP6SS_PWR_CTL_REG		0x030  macro
688 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
690 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
691 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
696 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
699 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
701 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
705 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
729 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
731 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
739 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
741 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
742 		val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
748 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
751 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
753 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
755 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
757 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
761 	writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5proc_reset()
1065 		val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5_mba_reclaim()
1068 		writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);  in q6v5_mba_reclaim()