Lines Matching +full:0 +full:x7f
16 #define MT6358_BUCK_MODE_AUTO 0
54 .enable_mask = BIT(0), \
58 .qi = BIT(0), \
106 .enable_mask = BIT(0), \
111 .qi = BIT(0), \
134 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
138 REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
142 REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
146 REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
197 0, 12,
205 0, 1, 2, 4, 5, 9, 11, 13,
225 0, 7, 9, 10, 11, 12,
271 if (ret != 0) { in mt6358_get_voltage_sel()
281 for (idx = 0; idx < info->desc.n_voltages; idx++) { in mt6358_get_voltage_sel()
295 if (ret != 0) { in mt6358_get_buck_voltage_sel()
314 if (ret != 0) { in mt6358_get_status()
354 if (ret != 0) { in mt6358_regulator_get_mode()
407 buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
410 buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
413 buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f,
416 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
419 buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
422 buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f,
425 buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f,
428 buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
431 buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f,
434 MT6358_LDO_VRF12_CON0, 0, 1200000),
436 MT6358_LDO_VIO18_CON0, 0, 1800000),
438 MT6358_LDO_VCAMIO_CON0, 0, 1800000),
439 MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
440 MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
441 MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
442 MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
444 MT6358_LDO_VAUX18_CON0, 0, 1800000),
446 MT6358_LDO_VBIF28_CON0, 0, 2800000),
447 MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
448 MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
449 MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
451 MT6358_LDO_VAUD28_CON0, 0, 2800000),
453 MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf),
455 MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
457 MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
459 MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
461 MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00),
463 MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
465 MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
467 MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00),
469 MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
472 0, MT6358_VCN33_ANA_CON0, 0x300),
475 0, MT6358_VCN33_ANA_CON0, 0x300),
477 MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00),
479 MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
481 MT6358_LDO_VLDO28_CON0_0, 0,
482 MT6358_VLDO28_ANA_CON0, 0x300),
484 MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
486 buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00,
487 MT6358_LDO_VSRAM_CON0, 0x7f),
489 buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00,
490 MT6358_LDO_VSRAM_CON2, 0x7f),
492 buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00,
493 MT6358_LDO_VSRAM_CON3, 0x7f),
495 buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00,
496 MT6358_LDO_VSRAM_CON1, 0x7f),
506 for (i = 0; i < MT6358_MAX_REGULATOR; i++) { in mt6358_regulator_probe()
521 return 0; in mt6358_regulator_probe()
525 {"mt6358-regulator", 0},