98 static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx)  in pwm_imx27_clk_prepare_enable()  argument
102 	ret = clk_prepare_enable(imx->clk_ipg);  in pwm_imx27_clk_prepare_enable()
106 	ret = clk_prepare_enable(imx->clk_per);  in pwm_imx27_clk_prepare_enable()
108 		clk_disable_unprepare(imx->clk_ipg);  in pwm_imx27_clk_prepare_enable()
115 static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx)  in pwm_imx27_clk_disable_unprepare()  argument
117 	clk_disable_unprepare(imx->clk_per);  in pwm_imx27_clk_disable_unprepare()
118 	clk_disable_unprepare(imx->clk_ipg);  in pwm_imx27_clk_disable_unprepare()
124 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_get_state()  local
129 	ret = pwm_imx27_clk_prepare_enable(imx);  in pwm_imx27_get_state()
133 	val = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_get_state()
152 	pwm_clk = clk_get_rate(imx->clk_per);  in pwm_imx27_get_state()
153 	val = readl(imx->mmio_base + MX3_PWMPR);  in pwm_imx27_get_state()
165 		val = readl(imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_get_state()
167 		val = imx->duty_cycle;  in pwm_imx27_get_state()
172 	pwm_imx27_clk_disable_unprepare(imx);  in pwm_imx27_get_state()
177 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_sw_reset()  local
182 	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);  in pwm_imx27_sw_reset()
185 		cr = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_sw_reset()
196 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_wait_fifo_slot()  local
202 	sr = readl(imx->mmio_base + MX3_PWMSR);  in pwm_imx27_wait_fifo_slot()
209 		sr = readl(imx->mmio_base + MX3_PWMSR);  in pwm_imx27_wait_fifo_slot()
219 	struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip);  in pwm_imx27_apply()  local
228 	clkrate = clk_get_rate(imx->clk_per);  in pwm_imx27_apply()
243 	 * according to imx pwm RM, the real period value should be PERIOD  in pwm_imx27_apply()
258 		ret = pwm_imx27_clk_prepare_enable(imx);  in pwm_imx27_apply()
265 	writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);  in pwm_imx27_apply()
266 	writel(period_cycles, imx->mmio_base + MX3_PWMPR);  in pwm_imx27_apply()
272 	imx->duty_cycle = duty_cycles;  in pwm_imx27_apply()
286 	writel(cr, imx->mmio_base + MX3_PWMCR);  in pwm_imx27_apply()
289 		pwm_imx27_clk_disable_unprepare(imx);  in pwm_imx27_apply()
308 	struct pwm_imx27_chip *imx;  in pwm_imx27_probe()  local
312 	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);  in pwm_imx27_probe()
313 	if (imx == NULL)  in pwm_imx27_probe()
316 	imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");  in pwm_imx27_probe()
317 	if (IS_ERR(imx->clk_ipg))  in pwm_imx27_probe()
318 		return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg),  in pwm_imx27_probe()
321 	imx->clk_per = devm_clk_get(&pdev->dev, "per");  in pwm_imx27_probe()
322 	if (IS_ERR(imx->clk_per))  in pwm_imx27_probe()
323 		return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per),  in pwm_imx27_probe()
326 	imx->chip.ops = &pwm_imx27_ops;  in pwm_imx27_probe()
327 	imx->chip.dev = &pdev->dev;  in pwm_imx27_probe()
328 	imx->chip.npwm = 1;  in pwm_imx27_probe()
330 	imx->mmio_base = devm_platform_ioremap_resource(pdev, 0);  in pwm_imx27_probe()
331 	if (IS_ERR(imx->mmio_base))  in pwm_imx27_probe()
332 		return PTR_ERR(imx->mmio_base);  in pwm_imx27_probe()
334 	ret = pwm_imx27_clk_prepare_enable(imx);  in pwm_imx27_probe()
339 	pwmcr = readl(imx->mmio_base + MX3_PWMCR);  in pwm_imx27_probe()
341 		pwm_imx27_clk_disable_unprepare(imx);  in pwm_imx27_probe()
343 	return devm_pwmchip_add(&pdev->dev, &imx->chip);  in pwm_imx27_probe()