1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #define PWM_CFG0_ADDR(x)    (((x) * 0x20) + 0x0)  argument
19 #define PWM_CFG1_ADDR(x)    (((x) * 0x20) + 0x4)  argument
20 #define PWM_CFG2_ADDR(x)    (((x) * 0x20) + 0x8)  argument
21 #define PWM_CTRL_ADDR(x)    (((x) * 0x20) + 0xC)  argument
38 	void __iomem *base;  member
71 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset,  in hibvt_pwm_set_bits()  argument
74 	void __iomem *address = base + offset;  in hibvt_pwm_set_bits()
87 	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),  in hibvt_pwm_enable()
95 	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),  in hibvt_pwm_disable()
105 	freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);  in hibvt_pwm_config()
107 	period = div_u64(freq * period_ns, 1000);  in hibvt_pwm_config()
110 	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm),  in hibvt_pwm_config()
113 	hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm),  in hibvt_pwm_config()
124 		hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),  in hibvt_pwm_set_polarity()
127 		hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm),  in hibvt_pwm_set_polarity()
135 	void __iomem *base;  in hibvt_pwm_get_state()  local
138 	freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000);  in hibvt_pwm_get_state()
139 	base = hi_pwm_chip->base;  in hibvt_pwm_get_state()
141 	value = readl(base + PWM_CFG0_ADDR(pwm->hwpwm));  in hibvt_pwm_get_state()
142 	state->period = div_u64(value * 1000, freq);  in hibvt_pwm_get_state()
144 	value = readl(base + PWM_CFG1_ADDR(pwm->hwpwm));  in hibvt_pwm_get_state()
145 	state->duty_cycle = div_u64(value * 1000, freq);  in hibvt_pwm_get_state()
147 	value = readl(base + PWM_CTRL_ADDR(pwm->hwpwm));  in hibvt_pwm_get_state()
148 	state->enabled = (PWM_ENABLE_MASK & value);  in hibvt_pwm_get_state()
156 	if (state->polarity != pwm->state.polarity)  in hibvt_pwm_apply()
157 		hibvt_pwm_set_polarity(chip, pwm, state->polarity);  in hibvt_pwm_apply()
159 	if (state->period != pwm->state.period ||  in hibvt_pwm_apply()
160 	    state->duty_cycle != pwm->state.duty_cycle) {  in hibvt_pwm_apply()
161 		hibvt_pwm_config(chip, pwm, state->duty_cycle, state->period);  in hibvt_pwm_apply()
167 		if (hi_pwm_chip->soc->quirk_force_enable && state->enabled)  in hibvt_pwm_apply()
171 	if (state->enabled != pwm->state.enabled) {  in hibvt_pwm_apply()
172 		if (state->enabled)  in hibvt_pwm_apply()
191 				of_device_get_match_data(&pdev->dev);  in hibvt_pwm_probe()
195 	pwm_chip = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip), GFP_KERNEL);  in hibvt_pwm_probe()
197 		return -ENOMEM;  in hibvt_pwm_probe()
199 	pwm_chip->clk = devm_clk_get(&pdev->dev, NULL);  in hibvt_pwm_probe()
200 	if (IS_ERR(pwm_chip->clk)) {  in hibvt_pwm_probe()
201 		dev_err(&pdev->dev, "getting clock failed with %ld\n",  in hibvt_pwm_probe()
202 				PTR_ERR(pwm_chip->clk));  in hibvt_pwm_probe()
203 		return PTR_ERR(pwm_chip->clk);  in hibvt_pwm_probe()
206 	pwm_chip->chip.ops = &hibvt_pwm_ops;  in hibvt_pwm_probe()
207 	pwm_chip->chip.dev = &pdev->dev;  in hibvt_pwm_probe()
208 	pwm_chip->chip.npwm = soc->num_pwms;  in hibvt_pwm_probe()
209 	pwm_chip->soc = soc;  in hibvt_pwm_probe()
211 	pwm_chip->base = devm_platform_ioremap_resource(pdev, 0);  in hibvt_pwm_probe()
212 	if (IS_ERR(pwm_chip->base))  in hibvt_pwm_probe()
213 		return PTR_ERR(pwm_chip->base);  in hibvt_pwm_probe()
215 	ret = clk_prepare_enable(pwm_chip->clk);  in hibvt_pwm_probe()
219 	pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in hibvt_pwm_probe()
220 	if (IS_ERR(pwm_chip->rstc)) {  in hibvt_pwm_probe()
221 		clk_disable_unprepare(pwm_chip->clk);  in hibvt_pwm_probe()
222 		return PTR_ERR(pwm_chip->rstc);  in hibvt_pwm_probe()
225 	reset_control_assert(pwm_chip->rstc);  in hibvt_pwm_probe()
227 	reset_control_deassert(pwm_chip->rstc);  in hibvt_pwm_probe()
229 	ret = pwmchip_add(&pwm_chip->chip);  in hibvt_pwm_probe()
231 		clk_disable_unprepare(pwm_chip->clk);  in hibvt_pwm_probe()
235 	for (i = 0; i < pwm_chip->chip.npwm; i++) {  in hibvt_pwm_probe()
236 		hibvt_pwm_set_bits(pwm_chip->base, PWM_CTRL_ADDR(i),  in hibvt_pwm_probe()
251 	pwmchip_remove(&pwm_chip->chip);  in hibvt_pwm_remove()
253 	reset_control_assert(pwm_chip->rstc);  in hibvt_pwm_remove()
255 	reset_control_deassert(pwm_chip->rstc);  in hibvt_pwm_remove()
257 	clk_disable_unprepare(pwm_chip->clk);  in hibvt_pwm_remove()
263 	{ .compatible = "hisilicon,hi3516cv300-pwm",
265 	{ .compatible = "hisilicon,hi3519v100-pwm",
267 	{ .compatible = "hisilicon,hi3559v100-shub-pwm",
269 	{ .compatible = "hisilicon,hi3559v100-pwm",
277 		.name = "hibvt-pwm",