39 #define IPROC_PWM_PRESCALE_SHIFT(ch)		((3 - (ch)) * \
61 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_enable()
63 	writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_enable()
65 	/* must be a 400 ns delay between clearing and setting enable bit */  in iproc_pwmc_enable()
73 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_disable()
75 	writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_disable()
77 	/* must be a 400 ns delay between clearing and setting enable bit */  in iproc_pwmc_disable()
85 	u64 tmp, multi, rate;  in iproc_pwmc_get_state()  local
88 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_get_state()
90 	if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm)))  in iproc_pwmc_get_state()
91 		state->enabled = true;  in iproc_pwmc_get_state()
93 		state->enabled = false;  in iproc_pwmc_get_state()
95 	if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm)))  in iproc_pwmc_get_state()
96 		state->polarity = PWM_POLARITY_NORMAL;  in iproc_pwmc_get_state()
98 		state->polarity = PWM_POLARITY_INVERSED;  in iproc_pwmc_get_state()
100 	rate = clk_get_rate(ip->clk);  in iproc_pwmc_get_state()
102 		state->period = 0;  in iproc_pwmc_get_state()
103 		state->duty_cycle = 0;  in iproc_pwmc_get_state()
107 	value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);  in iproc_pwmc_get_state()
108 	prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);  in iproc_pwmc_get_state()
111 	multi = NSEC_PER_SEC * (prescale + 1);  in iproc_pwmc_get_state()
113 	value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));  in iproc_pwmc_get_state()
114 	tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;  in iproc_pwmc_get_state()
115 	state->period = div64_u64(tmp, rate);  in iproc_pwmc_get_state()
117 	value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));  in iproc_pwmc_get_state()
118 	tmp = (value & IPROC_PWM_PERIOD_MAX) * multi;  in iproc_pwmc_get_state()
119 	state->duty_cycle = div64_u64(tmp, rate);  in iproc_pwmc_get_state()
130 	rate = clk_get_rate(ip->clk);  in iproc_pwmc_apply()
146 		value = rate * state->period;  in iproc_pwmc_apply()
148 		value = rate * state->duty_cycle;  in iproc_pwmc_apply()
152 			return -EINVAL;  in iproc_pwmc_apply()
160 			return -EINVAL;  in iproc_pwmc_apply()
163 	iproc_pwmc_disable(ip, pwm->hwpwm);  in iproc_pwmc_apply()
166 	value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET);  in iproc_pwmc_apply()
167 	value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm);  in iproc_pwmc_apply()
168 	value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm);  in iproc_pwmc_apply()
169 	writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET);  in iproc_pwmc_apply()
172 	writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm));  in iproc_pwmc_apply()
173 	writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm));  in iproc_pwmc_apply()
176 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_apply()
178 	if (state->polarity == PWM_POLARITY_NORMAL)  in iproc_pwmc_apply()
179 		value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm);  in iproc_pwmc_apply()
181 		value &= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm));  in iproc_pwmc_apply()
183 	writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_apply()
185 	if (state->enabled)  in iproc_pwmc_apply()
186 		iproc_pwmc_enable(ip, pwm->hwpwm);  in iproc_pwmc_apply()
204 	ip = devm_kzalloc(&pdev->dev, sizeof(*ip), GFP_KERNEL);  in iproc_pwmc_probe()
206 		return -ENOMEM;  in iproc_pwmc_probe()
210 	ip->chip.dev = &pdev->dev;  in iproc_pwmc_probe()
211 	ip->chip.ops = &iproc_pwm_ops;  in iproc_pwmc_probe()
212 	ip->chip.npwm = 4;  in iproc_pwmc_probe()
214 	ip->base = devm_platform_ioremap_resource(pdev, 0);  in iproc_pwmc_probe()
215 	if (IS_ERR(ip->base))  in iproc_pwmc_probe()
216 		return PTR_ERR(ip->base);  in iproc_pwmc_probe()
218 	ip->clk = devm_clk_get(&pdev->dev, NULL);  in iproc_pwmc_probe()
219 	if (IS_ERR(ip->clk)) {  in iproc_pwmc_probe()
220 		dev_err(&pdev->dev, "failed to get clock: %ld\n",  in iproc_pwmc_probe()
221 			PTR_ERR(ip->clk));  in iproc_pwmc_probe()
222 		return PTR_ERR(ip->clk);  in iproc_pwmc_probe()
225 	ret = clk_prepare_enable(ip->clk);  in iproc_pwmc_probe()
227 		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);  in iproc_pwmc_probe()
232 	value = readl(ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_probe()
234 	for (i = 0; i < ip->chip.npwm; i++) {  in iproc_pwmc_probe()
239 	writel(value, ip->base + IPROC_PWM_CTRL_OFFSET);  in iproc_pwmc_probe()
241 	ret = pwmchip_add(&ip->chip);  in iproc_pwmc_probe()
243 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);  in iproc_pwmc_probe()
244 		clk_disable_unprepare(ip->clk);  in iproc_pwmc_probe()
254 	pwmchip_remove(&ip->chip);  in iproc_pwmc_remove()
256 	clk_disable_unprepare(ip->clk);  in iproc_pwmc_remove()
262 	{ .compatible = "brcm,iproc-pwm" },
269 		.name = "bcm-iproc-pwm",