Lines Matching full:definitions

522 /* Bit definitions for the MAJ_REL register */
527 /* Bit definitions for the USER_GPIO0_TO_7_STATUS register */
537 /* Bit definitions for the USER_GPIO8_TO_15_STATUS register */
547 /* Bit definitions for the GPIO0_TO_7_OUT register */
557 /* Bit definitions for the GPIO8_TO_15_OUT register */
567 /* Bit definitions for the DPLL_TOD_SYNC_CFG register */
572 /* Bit definitions for the DPLL_MODE register */
579 /* Bit definitions for the GPIO_CFG_GBL register */
583 /* Bit definitions for the GPIO_DCO_INC_DEC register */
587 /* Bit definitions for the GPIO_OUT_CTRL_0 register */
597 /* Bit definitions for the GPIO_OUT_CTRL_1 register */
607 /* Bit definitions for the GPIO_TOD_TRIG register */
613 /* Bit definitions for the GPIO_DPLL_INDICATOR register */
617 /* Bit definitions for the GPIO_LOS_INDICATOR register */
623 /* Bit definitions for the GPIO_REF_INPUT_DSQ_0 register */
633 /* Bit definitions for the GPIO_REF_INPUT_DSQ_1 register */
643 /* Bit definitions for the GPIO_REF_INPUT_DSQ_2 register */
653 /* Bit definitions for the GPIO_REF_INPUT_DSQ_3 register */
657 /* Bit definitions for the GPIO_TOD_NOTIFICATION_CFG register */
663 /* Bit definitions for the GPIO_CTRL register */
671 /* Bit definitions for the OUT_CTRL_1 register */
680 /* Bit definitions for the TOD_CFG register */
685 /* Bit definitions for the TOD_WRITE_SELECT_CFG_0 register */
691 /* Bit definitions for the TOD_WRITE_CMD register */
698 /* Bit definitions for the TOD_READ_PRIMARY_SEL_CFG_0 register */
704 /* Bit definitions for the TOD_READ_PRIMARY_CMD register */
709 /* Bit definitions for the DPLL_CTRL_COMBO_MASTER_CFG register */
712 /* Bit definitions for DPLL_SYS_STATUS register */
715 /* Bit definitions for SYS_APLL_STATUS register */