153 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,  in stm32_gpio_backup_value()  argument
156 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);  in stm32_gpio_backup_value()
157 	bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;  in stm32_gpio_backup_value()
160 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_mode()  argument
163 	bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |  in stm32_gpio_backup_mode()
165 	bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;  in stm32_gpio_backup_mode()
166 	bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;  in stm32_gpio_backup_mode()
169 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_driving()  argument
172 	bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);  in stm32_gpio_backup_driving()
173 	bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;  in stm32_gpio_backup_driving()
176 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_speed()  argument
179 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;  in stm32_gpio_backup_speed()
180 	bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;  in stm32_gpio_backup_speed()
183 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,  in stm32_gpio_backup_bias()  argument
186 	bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;  in stm32_gpio_backup_bias()
187 	bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;  in stm32_gpio_backup_bias()
192 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,  in __stm32_gpio_set()  argument
195 	stm32_gpio_backup_value(bank, offset, value);  in __stm32_gpio_set()
200 	clk_enable(bank->clk);  in __stm32_gpio_set()
202 	writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);  in __stm32_gpio_set()
204 	clk_disable(bank->clk);  in __stm32_gpio_set()
209 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_request()  local
210 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_request()
212 	int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);  in stm32_gpio_request()
230 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_get()  local
233 	clk_enable(bank->clk);  in stm32_gpio_get()
235 	ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));  in stm32_gpio_get()
237 	clk_disable(bank->clk);  in stm32_gpio_get()
244 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_set()  local
246 	__stm32_gpio_set(bank, offset, value);  in stm32_gpio_set()
257 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_direction_output()  local
259 	__stm32_gpio_set(bank, offset, value);  in stm32_gpio_direction_output()
268 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_to_irq()  local
271 	fwspec.fwnode = bank->fwnode;  in stm32_gpio_to_irq()
281 	struct stm32_gpio_bank *bank = gpiochip_get_data(chip);  in stm32_gpio_get_direction()  local
286 	stm32_pmx_get_mode(bank, pin, &mode, &alt);  in stm32_gpio_get_direction()
311 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_irq_trigger()  local
315 	level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);  in stm32_gpio_irq_trigger()
316 	if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||  in stm32_gpio_irq_trigger()
317 	    (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))  in stm32_gpio_irq_trigger()
329 	struct stm32_gpio_bank *bank = d->domain->host_data;  in stm32_gpio_set_type()  local
348 	bank->irq_type[d->hwirq] = type;  in stm32_gpio_set_type()
355 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_request_resources()  local
356 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_irq_request_resources()
359 	ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
363 	ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_request_resources()
375 	struct stm32_gpio_bank *bank = irq_data->domain->host_data;  in stm32_gpio_irq_release_resources()  local
377 	gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);  in stm32_gpio_irq_release_resources()
415 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_activate()  local
416 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_activate()
428 	regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);  in stm32_gpio_domain_activate()
440 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_alloc()  local
443 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_alloc()
471 				      bank);  in stm32_gpio_domain_alloc()
479 	struct stm32_gpio_bank *bank = d->host_data;  in stm32_gpio_domain_free()  local
480 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_gpio_domain_free()
743 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,  in stm32_pmx_set_mode()  argument
746 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pmx_set_mode()
753 	clk_enable(bank->clk);  in stm32_pmx_set_mode()
754 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_set_mode()
765 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_set_mode()
768 	writel_relaxed(val, bank->base + alt_offset);  in stm32_pmx_set_mode()
770 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
773 	writel_relaxed(val, bank->base + STM32_GPIO_MODER);  in stm32_pmx_set_mode()
778 	stm32_gpio_backup_mode(bank, pin, mode, alt);  in stm32_pmx_set_mode()
781 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_set_mode()
782 	clk_disable(bank->clk);  in stm32_pmx_set_mode()
787 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,  in stm32_pmx_get_mode()  argument
795 	clk_enable(bank->clk);  in stm32_pmx_get_mode()
796 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pmx_get_mode()
798 	val = readl_relaxed(bank->base + alt_offset);  in stm32_pmx_get_mode()
802 	val = readl_relaxed(bank->base + STM32_GPIO_MODER);  in stm32_pmx_get_mode()
806 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pmx_get_mode()
807 	clk_disable(bank->clk);  in stm32_pmx_get_mode()
818 	struct stm32_gpio_bank *bank;  in stm32_pmx_set_mux()  local
832 	bank = gpiochip_get_data(range->gc);  in stm32_pmx_set_mux()
838 	return stm32_pmx_set_mode(bank, pin, mode, alt);  in stm32_pmx_set_mux()
845 	struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);  in stm32_pmx_gpio_set_direction()  local
848 	return stm32_pmx_set_mode(bank, pin, !input, 0);  in stm32_pmx_gpio_set_direction()
862 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,  in stm32_pconf_set_driving()  argument
865 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_driving()
870 	clk_enable(bank->clk);  in stm32_pconf_set_driving()
871 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_driving()
882 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
885 	writel_relaxed(val, bank->base + STM32_GPIO_TYPER);  in stm32_pconf_set_driving()
890 	stm32_gpio_backup_driving(bank, offset, drive);  in stm32_pconf_set_driving()
893 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_driving()
894 	clk_disable(bank->clk);  in stm32_pconf_set_driving()
899 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,  in stm32_pconf_get_driving()  argument
905 	clk_enable(bank->clk);  in stm32_pconf_get_driving()
906 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_driving()
908 	val = readl_relaxed(bank->base + STM32_GPIO_TYPER);  in stm32_pconf_get_driving()
911 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_driving()
912 	clk_disable(bank->clk);  in stm32_pconf_get_driving()
917 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,  in stm32_pconf_set_speed()  argument
920 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_speed()
925 	clk_enable(bank->clk);  in stm32_pconf_set_speed()
926 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_speed()
937 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
940 	writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_set_speed()
945 	stm32_gpio_backup_speed(bank, offset, speed);  in stm32_pconf_set_speed()
948 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_speed()
949 	clk_disable(bank->clk);  in stm32_pconf_set_speed()
954 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,  in stm32_pconf_get_speed()  argument
960 	clk_enable(bank->clk);  in stm32_pconf_get_speed()
961 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_speed()
963 	val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);  in stm32_pconf_get_speed()
966 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_speed()
967 	clk_disable(bank->clk);  in stm32_pconf_get_speed()
972 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,  in stm32_pconf_set_bias()  argument
975 	struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);  in stm32_pconf_set_bias()
980 	clk_enable(bank->clk);  in stm32_pconf_set_bias()
981 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_set_bias()
992 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
995 	writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_set_bias()
1000 	stm32_gpio_backup_bias(bank, offset, bias);  in stm32_pconf_set_bias()
1003 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_set_bias()
1004 	clk_disable(bank->clk);  in stm32_pconf_set_bias()
1009 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,  in stm32_pconf_get_bias()  argument
1015 	clk_enable(bank->clk);  in stm32_pconf_get_bias()
1016 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get_bias()
1018 	val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);  in stm32_pconf_get_bias()
1021 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get_bias()
1022 	clk_disable(bank->clk);  in stm32_pconf_get_bias()
1027 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,  in stm32_pconf_get()  argument
1033 	clk_enable(bank->clk);  in stm32_pconf_get()
1034 	spin_lock_irqsave(&bank->lock, flags);  in stm32_pconf_get()
1037 		val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &  in stm32_pconf_get()
1040 		val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &  in stm32_pconf_get()
1043 	spin_unlock_irqrestore(&bank->lock, flags);  in stm32_pconf_get()
1044 	clk_disable(bank->clk);  in stm32_pconf_get()
1055 	struct stm32_gpio_bank *bank;  in stm32_pconf_parse_conf()  local
1064 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_parse_conf()
1069 		ret = stm32_pconf_set_driving(bank, offset, 0);  in stm32_pconf_parse_conf()
1072 		ret = stm32_pconf_set_driving(bank, offset, 1);  in stm32_pconf_parse_conf()
1075 		ret = stm32_pconf_set_speed(bank, offset, arg);  in stm32_pconf_parse_conf()
1078 		ret = stm32_pconf_set_bias(bank, offset, 0);  in stm32_pconf_parse_conf()
1081 		ret = stm32_pconf_set_bias(bank, offset, 1);  in stm32_pconf_parse_conf()
1084 		ret = stm32_pconf_set_bias(bank, offset, 2);  in stm32_pconf_parse_conf()
1087 		__stm32_gpio_set(bank, offset, arg);  in stm32_pconf_parse_conf()
1151 	struct stm32_gpio_bank *bank;  in stm32_pconf_dbg_show()  local
1166 	bank = gpiochip_get_data(range->gc);  in stm32_pconf_dbg_show()
1169 	stm32_pmx_get_mode(bank, offset, &mode, &alt);  in stm32_pconf_dbg_show()
1170 	bias = stm32_pconf_get_bias(bank, offset);  in stm32_pconf_dbg_show()
1177 		val = stm32_pconf_get(bank, offset, true);  in stm32_pconf_dbg_show()
1185 		drive = stm32_pconf_get_driving(bank, offset);  in stm32_pconf_dbg_show()
1186 		speed = stm32_pconf_get_speed(bank, offset);  in stm32_pconf_dbg_show()
1187 		val = stm32_pconf_get(bank, offset, false);  in stm32_pconf_dbg_show()
1197 		drive = stm32_pconf_get_driving(bank, offset);  in stm32_pconf_dbg_show()
1198 		speed = stm32_pconf_get_speed(bank, offset);  in stm32_pconf_dbg_show()
1221 	struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];  in stm32_gpiolib_register_bank()  local
1223 	struct pinctrl_gpio_range *range = &bank->range;  in stm32_gpiolib_register_bank()
1230 	if (!IS_ERR(bank->rstc))  in stm32_gpiolib_register_bank()
1231 		reset_control_deassert(bank->rstc);  in stm32_gpiolib_register_bank()
1236 	bank->base = devm_ioremap_resource(dev, &res);  in stm32_gpiolib_register_bank()
1237 	if (IS_ERR(bank->base))  in stm32_gpiolib_register_bank()
1238 		return PTR_ERR(bank->base);  in stm32_gpiolib_register_bank()
1240 	err = clk_prepare(bank->clk);  in stm32_gpiolib_register_bank()
1246 	bank->gpio_chip = stm32_gpio_template;  in stm32_gpiolib_register_bank()
1248 	of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1252 		bank->gpio_chip.base = args.args[1];  in stm32_gpiolib_register_bank()
1260 		bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1261 		range->name = bank->gpio_chip.label;  in stm32_gpiolib_register_bank()
1266 		range->gc = &bank->gpio_chip;  in stm32_gpiolib_register_bank()
1271 	if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))  in stm32_gpiolib_register_bank()
1274 	bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;  in stm32_gpiolib_register_bank()
1276 	bank->gpio_chip.ngpio = npins;  in stm32_gpiolib_register_bank()
1277 	bank->gpio_chip.of_node = np;  in stm32_gpiolib_register_bank()
1278 	bank->gpio_chip.parent = dev;  in stm32_gpiolib_register_bank()
1279 	bank->bank_nr = bank_nr;  in stm32_gpiolib_register_bank()
1280 	bank->bank_ioport_nr = bank_ioport_nr;  in stm32_gpiolib_register_bank()
1281 	spin_lock_init(&bank->lock);  in stm32_gpiolib_register_bank()
1284 	bank->fwnode = of_node_to_fwnode(np);  in stm32_gpiolib_register_bank()
1286 	bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,  in stm32_gpiolib_register_bank()
1287 					STM32_GPIO_IRQ_LINE, bank->fwnode,  in stm32_gpiolib_register_bank()
1288 					&stm32_gpio_domain_ops, bank);  in stm32_gpiolib_register_bank()
1290 	if (!bank->domain)  in stm32_gpiolib_register_bank()
1293 	err = gpiochip_add_data(&bank->gpio_chip, bank);  in stm32_gpiolib_register_bank()
1299 	dev_info(dev, "%s bank added\n", bank->gpio_chip.label);  in stm32_gpiolib_register_bank()
1531 		dev_err(dev, "at least one GPIO bank is required\n");  in stm32_pctl_probe()
1541 		struct stm32_gpio_bank *bank = &pctl->banks[i];  in stm32_pctl_probe()  local
1544 			bank->rstc = of_reset_control_get_exclusive(child,  in stm32_pctl_probe()
1546 			if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {  in stm32_pctl_probe()
1551 			bank->clk = of_clk_get_by_name(child, NULL);  in stm32_pctl_probe()
1552 			if (IS_ERR(bank->clk)) {  in stm32_pctl_probe()
1553 				if (PTR_ERR(bank->clk) != -EPROBE_DEFER)  in stm32_pctl_probe()
1556 						PTR_ERR(bank->clk));  in stm32_pctl_probe()
1558 				return PTR_ERR(bank->clk);  in stm32_pctl_probe()
1587 	struct stm32_gpio_bank *bank;  in stm32_pinctrl_restore_gpio_regs()  local
1600 	bank = gpiochip_get_data(range->gc);  in stm32_pinctrl_restore_gpio_regs()
1602 	alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;  in stm32_pinctrl_restore_gpio_regs()
1604 	mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;  in stm32_pinctrl_restore_gpio_regs()
1607 	ret = stm32_pmx_set_mode(bank, offset, mode, alt);  in stm32_pinctrl_restore_gpio_regs()
1612 		val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);  in stm32_pinctrl_restore_gpio_regs()
1614 		__stm32_gpio_set(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1617 	val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);  in stm32_pinctrl_restore_gpio_regs()
1619 	ret = stm32_pconf_set_driving(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1623 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;  in stm32_pinctrl_restore_gpio_regs()
1625 	ret = stm32_pconf_set_speed(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1629 	val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;  in stm32_pinctrl_restore_gpio_regs()
1631 	ret = stm32_pconf_set_bias(bank, offset, val);  in stm32_pinctrl_restore_gpio_regs()
1636 		regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);  in stm32_pinctrl_restore_gpio_regs()