637 	struct exynos_eint_gpio_save *save = bank->soc_priv;  in exynos_pinctrl_suspend_bank()  local
640 	save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET  in exynos_pinctrl_suspend_bank()
642 	save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET  in exynos_pinctrl_suspend_bank()
644 	save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET  in exynos_pinctrl_suspend_bank()
646 	save->eint_mask = readl(regs + bank->irq_chip->eint_mask  in exynos_pinctrl_suspend_bank()
649 	pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);  in exynos_pinctrl_suspend_bank()
650 	pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);  in exynos_pinctrl_suspend_bank()
651 	pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);  in exynos_pinctrl_suspend_bank()
652 	pr_debug("%s: save    mask %#010x\n", bank->name, save->eint_mask);  in exynos_pinctrl_suspend_bank()
678 	struct exynos_eint_gpio_save *save = bank->soc_priv;  in exynos_pinctrl_resume_bank()  local
683 			+ bank->eint_offset), save->eint_con);  in exynos_pinctrl_resume_bank()
686 			+ 2 * bank->eint_offset), save->eint_fltcon0);  in exynos_pinctrl_resume_bank()
689 			+ 2 * bank->eint_offset + 4), save->eint_fltcon1);  in exynos_pinctrl_resume_bank()
692 			+ bank->eint_offset), save->eint_mask);  in exynos_pinctrl_resume_bank()
694 	writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET  in exynos_pinctrl_resume_bank()
696 	writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET  in exynos_pinctrl_resume_bank()
698 	writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET  in exynos_pinctrl_resume_bank()
700 	writel(save->eint_mask, regs + bank->irq_chip->eint_mask  in exynos_pinctrl_resume_bank()