8 #define DRV_NAME "sh-pfc"
38 	struct sh_pfc *pfc;  member
52 	return pmx->pfc->info->nr_groups;  in sh_pfc_get_groups_count()
60 	return pmx->pfc->info->groups[selector].name;  in sh_pfc_get_group_name()
68 	*pins = pmx->pfc->info->groups[selector].pins;  in sh_pfc_get_group_pins()
69 	*num_pins = pmx->pfc->info->groups[selector].nr_pins;  in sh_pfc_get_group_pins()
108 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_subnode_to_map()
263 	struct device *dev = pmx->pfc->dev;  in sh_pfc_dt_node_to_map()
318 	return pmx->pfc->info->nr_functions;  in sh_pfc_get_functions_count()
326 	return pmx->pfc->info->functions[selector].name;  in sh_pfc_get_function_name()
336 	*groups = pmx->pfc->info->functions[selector].groups;  in sh_pfc_get_function_groups()
337 	*num_groups = pmx->pfc->info->functions[selector].nr_groups;  in sh_pfc_get_function_groups()
346 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_func_set_mux()  local
347 	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];  in sh_pfc_func_set_mux()
354 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_func_set_mux()
357 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
369 		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);  in sh_pfc_func_set_mux()
376 		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);  in sh_pfc_func_set_mux()
383 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_func_set_mux()
392 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_request_enable()  local
393 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_request_enable()
398 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
400 	if (!pfc->gpio) {  in sh_pfc_gpio_request_enable()
404 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_request_enable()
406 		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);  in sh_pfc_gpio_request_enable()
416 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_request_enable()
426 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_disable_free()  local
427 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_disable_free()
431 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
435 		sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);  in sh_pfc_gpio_disable_free()
436 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_disable_free()
445 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_gpio_set_direction()  local
447 	int idx = sh_pfc_get_pin_index(pfc, offset);  in sh_pfc_gpio_set_direction()
448 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_gpio_set_direction()
462 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
463 	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);  in sh_pfc_gpio_set_direction()
464 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_gpio_set_direction()
481 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,  in sh_pfc_pinconf_find_drive_strength_reg()  argument
488 	for (reg = pfc->info->drive_regs; reg->reg; ++reg) {  in sh_pfc_pinconf_find_drive_strength_reg()
504 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_get_drive_strength()  argument
513 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_get_drive_strength()
517 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get_drive_strength()
518 	val = sh_pfc_read(pfc, reg);  in sh_pfc_pinconf_get_drive_strength()
519 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get_drive_strength()
529 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,  in sh_pfc_pinconf_set_drive_strength()  argument
539 	reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);  in sh_pfc_pinconf_set_drive_strength()
553 	spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
555 	val = sh_pfc_read(pfc, reg);  in sh_pfc_pinconf_set_drive_strength()
559 	sh_pfc_write(pfc, reg, val);  in sh_pfc_pinconf_set_drive_strength()
561 	spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set_drive_strength()
567 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,  in sh_pfc_pinconf_validate()  argument
570 	int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_validate()
571 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_validate()
598 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_get()  local
603 	if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_get()
612 		if (!pfc->info->ops || !pfc->info->ops->get_bias)  in sh_pfc_pinconf_get()
615 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
616 		bias = pfc->info->ops->get_bias(pfc, _pin);  in sh_pfc_pinconf_get()
617 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
629 		ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);  in sh_pfc_pinconf_get()
638 		int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_get()
639 		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_get()
644 		if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_get()
647 		bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);  in sh_pfc_pinconf_get()
651 		spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_get()
652 		val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_get()
653 		spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_get()
674 	struct sh_pfc *pfc = pmx->pfc;  in sh_pfc_pinconf_set()  local
682 		if (!sh_pfc_pinconf_validate(pfc, _pin, param))  in sh_pfc_pinconf_set()
689 			if (!pfc->info->ops || !pfc->info->ops->set_bias)  in sh_pfc_pinconf_set()
692 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
693 			pfc->info->ops->set_bias(pfc, _pin, param);  in sh_pfc_pinconf_set()
694 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
703 			ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);  in sh_pfc_pinconf_set()
712 			int idx = sh_pfc_get_pin_index(pfc, _pin);  in sh_pfc_pinconf_set()
713 			const struct sh_pfc_pin *pin = &pfc->info->pins[idx];  in sh_pfc_pinconf_set()
718 			if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)  in sh_pfc_pinconf_set()
721 			bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);  in sh_pfc_pinconf_set()
731 			spin_lock_irqsave(&pfc->lock, flags);  in sh_pfc_pinconf_set()
732 			val = sh_pfc_read(pfc, pocctrl);  in sh_pfc_pinconf_set()
737 			sh_pfc_write(pfc, pocctrl, val);  in sh_pfc_pinconf_set()
738 			spin_unlock_irqrestore(&pfc->lock, flags);  in sh_pfc_pinconf_set()
760 	pins = pmx->pfc->info->groups[group].pins;  in sh_pfc_pinconf_group_set()
761 	num_pins = pmx->pfc->info->groups[group].nr_pins;  in sh_pfc_pinconf_group_set()
780 /* PFC ranges -> pinctrl pin descs */
781 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)  in sh_pfc_map_pins()  argument
786 	pmx->pins = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
787 				 pfc->info->nr_pins, sizeof(*pmx->pins),  in sh_pfc_map_pins()
792 	pmx->configs = devm_kcalloc(pfc->dev,  in sh_pfc_map_pins()
793 				    pfc->info->nr_pins, sizeof(*pmx->configs),  in sh_pfc_map_pins()
798 	for (i = 0; i < pfc->info->nr_pins; ++i) {  in sh_pfc_map_pins()
799 		const struct sh_pfc_pin *info = &pfc->info->pins[i];  in sh_pfc_map_pins()
810 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)  in sh_pfc_register_pinctrl()  argument
815 	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);  in sh_pfc_register_pinctrl()
819 	pmx->pfc = pfc;  in sh_pfc_register_pinctrl()
821 	ret = sh_pfc_map_pins(pfc, pmx);  in sh_pfc_register_pinctrl()
831 	pmx->pctl_desc.npins = pfc->info->nr_pins;  in sh_pfc_register_pinctrl()
833 	ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,  in sh_pfc_register_pinctrl()
836 		dev_err(pfc->dev, "could not register: %i\n", ret);  in sh_pfc_register_pinctrl()
845 rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,  in rcar_pin_to_bias_reg()  argument
850 	for (i = 0; pfc->info->bias_regs[i].puen || pfc->info->bias_regs[i].pud; i++) {  in rcar_pin_to_bias_reg()
851 		for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {  in rcar_pin_to_bias_reg()
852 			if (pfc->info->bias_regs[i].pins[j] == pin) {  in rcar_pin_to_bias_reg()
854 				return &pfc->info->bias_regs[i];  in rcar_pin_to_bias_reg()
864 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)  in rcar_pinmux_get_bias()  argument
869 	reg = rcar_pin_to_bias_reg(pfc, pin, &bit);  in rcar_pinmux_get_bias()
874 		if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))  in rcar_pinmux_get_bias()
876 		else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))  in rcar_pinmux_get_bias()
881 		if (sh_pfc_read(pfc, reg->pud) & BIT(bit))  in rcar_pinmux_get_bias()
888 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,  in rcar_pinmux_set_bias()  argument
895 	reg = rcar_pin_to_bias_reg(pfc, pin, &bit);  in rcar_pinmux_set_bias()
900 		enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);  in rcar_pinmux_set_bias()
905 				updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);  in rcar_pinmux_set_bias()
909 				sh_pfc_write(pfc, reg->pud, updown);  in rcar_pinmux_set_bias()
912 		sh_pfc_write(pfc, reg->puen, enable);  in rcar_pinmux_set_bias()
914 		enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);  in rcar_pinmux_set_bias()
918 		sh_pfc_write(pfc, reg->pud, enable);  in rcar_pinmux_set_bias()
927 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)  in rmobile_pinmux_get_bias()  argument
929 	void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin);  in rmobile_pinmux_get_bias()
943 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,  in rmobile_pinmux_set_bias()  argument
946 	void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin);  in rmobile_pinmux_set_bias()