Lines Matching full:pctrl
140 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, in rzg2l_pinctrl_set_pfc_mode() argument
146 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
149 reg = readw(pctrl->base + PM(port)); in rzg2l_pinctrl_set_pfc_mode()
151 writew(reg, pctrl->base + PM(port)); in rzg2l_pinctrl_set_pfc_mode()
154 reg = readb(pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
155 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
158 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ in rzg2l_pinctrl_set_pfc_mode()
159 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ in rzg2l_pinctrl_set_pfc_mode()
162 reg = readl(pctrl->base + PFC(port)); in rzg2l_pinctrl_set_pfc_mode()
164 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); in rzg2l_pinctrl_set_pfc_mode()
167 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ in rzg2l_pinctrl_set_pfc_mode()
168 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ in rzg2l_pinctrl_set_pfc_mode()
171 reg = readb(pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
172 writeb(reg | BIT(pin), pctrl->base + PMC(port)); in rzg2l_pinctrl_set_pfc_mode()
174 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_set_pfc_mode()
181 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_set_mux() local
198 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", in rzg2l_pinctrl_set_mux()
201 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), in rzg2l_pinctrl_set_mux()
235 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_subnode_to_map() local
258 dev_err(pctrl->dev, "Invalid pins list in DT\n"); in rzg2l_dt_subnode_to_map()
268 dev_err(pctrl->dev, in rzg2l_dt_subnode_to_map()
278 dev_err(pctrl->dev, "DT node must contain a config\n"); in rzg2l_dt_subnode_to_map()
311 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
312 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), in rzg2l_dt_subnode_to_map()
314 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); in rzg2l_dt_subnode_to_map()
355 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); in rzg2l_dt_subnode_to_map()
389 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_dt_node_to_map() local
417 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); in rzg2l_dt_node_to_map()
431 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_get() local
433 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_get()
455 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_get()
457 addr = pctrl->base + IEN(port); in rzg2l_pinctrl_pinconf_get()
465 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_get()
480 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_get()
481 addr = pctrl->base + pwr_reg; in rzg2l_pinctrl_pinconf_get()
483 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_get()
501 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in rzg2l_pinctrl_pinconf_set() local
502 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; in rzg2l_pinctrl_pinconf_set()
532 addr = pctrl->base + IEN(port); in rzg2l_pinctrl_pinconf_set()
538 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_set()
541 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_set()
561 addr = pctrl->base + pwr_reg; in rzg2l_pinctrl_pinconf_set()
562 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_set()
564 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_pinctrl_pinconf_set()
652 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_request() local
663 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_request()
666 reg8 = readb(pctrl->base + PMC(port)); in rzg2l_gpio_request()
668 writeb(reg8, pctrl->base + PMC(port)); in rzg2l_gpio_request()
670 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_request()
675 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, in rzg2l_gpio_set_direction() argument
681 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
683 reg16 = readw(pctrl->base + PM(port)); in rzg2l_gpio_set_direction()
687 writew(reg16, pctrl->base + PM(port)); in rzg2l_gpio_set_direction()
689 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set_direction()
694 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get_direction() local
698 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { in rzg2l_gpio_get_direction()
701 reg16 = readw(pctrl->base + PM(port)); in rzg2l_gpio_get_direction()
713 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_input() local
717 rzg2l_gpio_set_direction(pctrl, port, bit, false); in rzg2l_gpio_direction_input()
725 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_set() local
731 spin_lock_irqsave(&pctrl->lock, flags); in rzg2l_gpio_set()
733 reg8 = readb(pctrl->base + P(port)); in rzg2l_gpio_set()
736 writeb(reg8 | BIT(bit), pctrl->base + P(port)); in rzg2l_gpio_set()
738 writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); in rzg2l_gpio_set()
740 spin_unlock_irqrestore(&pctrl->lock, flags); in rzg2l_gpio_set()
746 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_direction_output() local
751 rzg2l_gpio_set_direction(pctrl, port, bit, true); in rzg2l_gpio_direction_output()
758 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); in rzg2l_gpio_get() local
763 reg16 = readw(pctrl->base + PM(port)); in rzg2l_gpio_get()
767 return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); in rzg2l_gpio_get()
769 return !!(readb(pctrl->base + P(port)) & BIT(bit)); in rzg2l_gpio_get()
968 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) in rzg2l_gpio_register() argument
970 struct device_node *np = pctrl->dev->of_node; in rzg2l_gpio_register()
971 struct gpio_chip *chip = &pctrl->gpio_chip; in rzg2l_gpio_register()
972 const char *name = dev_name(pctrl->dev); in rzg2l_gpio_register()
978 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); in rzg2l_gpio_register()
984 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); in rzg2l_gpio_register()
997 chip->parent = pctrl->dev; in rzg2l_gpio_register()
1002 pctrl->gpio_range.id = 0; in rzg2l_gpio_register()
1003 pctrl->gpio_range.pin_base = 0; in rzg2l_gpio_register()
1004 pctrl->gpio_range.base = 0; in rzg2l_gpio_register()
1005 pctrl->gpio_range.npins = chip->ngpio; in rzg2l_gpio_register()
1006 pctrl->gpio_range.name = chip->label; in rzg2l_gpio_register()
1007 pctrl->gpio_range.gc = chip; in rzg2l_gpio_register()
1008 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); in rzg2l_gpio_register()
1010 dev_err(pctrl->dev, "failed to add GPIO controller\n"); in rzg2l_gpio_register()
1014 dev_dbg(pctrl->dev, "Registered gpio controller\n"); in rzg2l_gpio_register()
1019 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) in rzg2l_pinctrl_register() argument
1026 pctrl->desc.name = DRV_NAME; in rzg2l_pinctrl_register()
1027 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; in rzg2l_pinctrl_register()
1028 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; in rzg2l_pinctrl_register()
1029 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; in rzg2l_pinctrl_register()
1030 pctrl->desc.confops = &rzg2l_pinctrl_confops; in rzg2l_pinctrl_register()
1031 pctrl->desc.owner = THIS_MODULE; in rzg2l_pinctrl_register()
1033 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); in rzg2l_pinctrl_register()
1037 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, in rzg2l_pinctrl_register()
1042 pctrl->pins = pins; in rzg2l_pinctrl_register()
1043 pctrl->desc.pins = pins; in rzg2l_pinctrl_register()
1045 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { in rzg2l_pinctrl_register()
1047 pins[i].name = pctrl->data->port_pins[i]; in rzg2l_pinctrl_register()
1050 pin_data[i] = pctrl->data->port_pin_configs[j]; in rzg2l_pinctrl_register()
1054 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { in rzg2l_pinctrl_register()
1055 unsigned int index = pctrl->data->n_port_pins + i; in rzg2l_pinctrl_register()
1058 pins[index].name = pctrl->data->dedicated_pins[i].name; in rzg2l_pinctrl_register()
1059 pin_data[index] = pctrl->data->dedicated_pins[i].config; in rzg2l_pinctrl_register()
1063 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, in rzg2l_pinctrl_register()
1064 &pctrl->pctl); in rzg2l_pinctrl_register()
1066 dev_err(pctrl->dev, "pinctrl registration failed\n"); in rzg2l_pinctrl_register()
1070 ret = pinctrl_enable(pctrl->pctl); in rzg2l_pinctrl_register()
1072 dev_err(pctrl->dev, "pinctrl enable failed\n"); in rzg2l_pinctrl_register()
1076 ret = rzg2l_gpio_register(pctrl); in rzg2l_pinctrl_register()
1078 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); in rzg2l_pinctrl_register()
1092 struct rzg2l_pinctrl *pctrl; in rzg2l_pinctrl_probe() local
1095 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in rzg2l_pinctrl_probe()
1096 if (!pctrl) in rzg2l_pinctrl_probe()
1099 pctrl->dev = &pdev->dev; in rzg2l_pinctrl_probe()
1101 pctrl->data = of_device_get_match_data(&pdev->dev); in rzg2l_pinctrl_probe()
1102 if (!pctrl->data) in rzg2l_pinctrl_probe()
1105 pctrl->base = devm_platform_ioremap_resource(pdev, 0); in rzg2l_pinctrl_probe()
1106 if (IS_ERR(pctrl->base)) in rzg2l_pinctrl_probe()
1107 return PTR_ERR(pctrl->base); in rzg2l_pinctrl_probe()
1109 pctrl->clk = devm_clk_get(pctrl->dev, NULL); in rzg2l_pinctrl_probe()
1110 if (IS_ERR(pctrl->clk)) { in rzg2l_pinctrl_probe()
1111 ret = PTR_ERR(pctrl->clk); in rzg2l_pinctrl_probe()
1112 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); in rzg2l_pinctrl_probe()
1116 spin_lock_init(&pctrl->lock); in rzg2l_pinctrl_probe()
1118 platform_set_drvdata(pdev, pctrl); in rzg2l_pinctrl_probe()
1120 ret = clk_prepare_enable(pctrl->clk); in rzg2l_pinctrl_probe()
1122 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); in rzg2l_pinctrl_probe()
1127 pctrl->clk); in rzg2l_pinctrl_probe()
1129 dev_err(pctrl->dev, in rzg2l_pinctrl_probe()
1135 ret = rzg2l_pinctrl_register(pctrl); in rzg2l_pinctrl_probe()
1139 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); in rzg2l_pinctrl_probe()