Lines Matching +full:0 +full:- +full:4
1 // SPDX-License-Identifier: GPL-2.0
3 * R8A77470 processor support - PFC hardware block.
14 PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
15 PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
29 PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
30 PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
31 PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
32 PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
33 PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
40 PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
41 PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
42 PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
43 PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
44 PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
45 PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
46 PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \
47 PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
48 PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
49 PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
50 PORT_GP_CFG_1(4, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
51 PORT_GP_CFG_1(4, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
52 PORT_GP_CFG_1(4, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
66 PINMUX_RESERVED = 0,
1147 /* - AVB -------------------------------------------------------------------- */
1188 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1189 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
1206 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1209 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
1212 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1213 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1251 /* - DU --------------------------------------------------------------------- */
1255 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1270 /* R[7:0], G[7:0], B[7:0] */
1272 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1273 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
1340 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1341 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1342 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1343 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1344 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1345 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1356 /* R[7:0], G[7:0], B[7:0] */
1357 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1358 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1359 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1360 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1361 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1362 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1363 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1364 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1365 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1384 RCAR_GP_PIN(5, 0),
1398 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
1424 /* - I2C0 ------------------------------------------------------------------- */
1427 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1460 /* - I2C1 ------------------------------------------------------------------- */
1463 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1477 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1491 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1496 /* - I2C2 ------------------------------------------------------------------- */
1499 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
1513 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1520 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1525 /* - I2C3 ------------------------------------------------------------------- */
1535 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1561 /* - I2C4 ------------------------------------------------------------------- */
1564 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1578 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1597 /* - MMC -------------------------------------------------------------------- */
1600 RCAR_GP_PIN(0, 15),
1606 /* D[0:3] */
1607 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1608 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1615 /* D[0:3] */
1616 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1617 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1618 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
1619 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
1629 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1634 /* - QSPI ------------------------------------------------------------------- */
1660 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
1667 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1674 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1675 RCAR_GP_PIN(4, 8),
1681 /* - SCIF0 ------------------------------------------------------------------ */
1684 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1698 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1710 /* - SCIF1 ------------------------------------------------------------------ */
1713 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1720 RCAR_GP_PIN(4, 15),
1755 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1760 /* - SCIF2 ------------------------------------------------------------------ */
1763 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1770 RCAR_GP_PIN(4, 20),
1796 /* - SCIF3 ------------------------------------------------------------------ */
1799 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1806 RCAR_GP_PIN(4, 21),
1820 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1825 /* - SCIF4 ------------------------------------------------------------------ */
1828 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1856 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1861 /* - SCIF5 ------------------------------------------------------------------ */
1864 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1871 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1878 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1892 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1904 /* - SCIF Clock ------------------------------------------------------------- */
1919 /* - SDHI0 ------------------------------------------------------------------ */
1922 RCAR_GP_PIN(0, 7),
1928 /* D[0:3] */
1929 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1930 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1937 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1944 RCAR_GP_PIN(0, 11),
1951 RCAR_GP_PIN(0, 12),
1956 /* - SDHI1 ------------------------------------------------------------------ */
1959 RCAR_GP_PIN(0, 15),
1965 /* D[0:3] */
1966 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1967 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1975 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1982 RCAR_GP_PIN(0, 19),
1989 RCAR_GP_PIN(0, 20),
1994 /* - SDHI2 ------------------------------------------------------------------ */
1997 RCAR_GP_PIN(4, 16),
2003 /* D[0:3] */
2004 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2005 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
2012 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2019 RCAR_GP_PIN(4, 20),
2026 RCAR_GP_PIN(4, 21),
2031 /* - USB0 ------------------------------------------------------------------- */
2033 RCAR_GP_PIN(0, 0), /* PWEN */
2034 RCAR_GP_PIN(0, 1), /* OVC */
2040 /* - USB1 ------------------------------------------------------------------- */
2042 RCAR_GP_PIN(0, 2), /* PWEN */
2043 RCAR_GP_PIN(0, 3), /* OVC */
2049 /* - VIN0 ------------------------------------------------------------------- */
2058 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2059 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2060 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2094 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2095 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2142 /* - VIN1 ------------------------------------------------------------------- */
2146 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2184 RCAR_GP_PIN(3, 0),
2563 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
2564 0, 0,
2565 0, 0,
2566 0, 0,
2567 0, 0,
2568 0, 0,
2569 0, 0,
2570 0, 0,
2571 0, 0,
2572 0, 0,
2597 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2598 0, 0,
2599 0, 0,
2600 0, 0,
2601 0, 0,
2602 0, 0,
2603 0, 0,
2604 0, 0,
2605 0, 0,
2606 0, 0,
2631 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2665 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2666 0, 0,
2667 0, 0,
2671 0, 0,
2672 0, 0,
2673 0, 0,
2674 0, 0,
2675 0, 0,
2676 0, 0,
2677 0, 0,
2678 0, 0,
2679 0, 0,
2680 0, 0,
2699 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2700 0, 0,
2701 0, 0,
2702 0, 0,
2703 0, 0,
2704 0, 0,
2705 0, 0,
2733 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2767 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2768 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2770 /* IP0_31_28 [4] */
2771 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
2772 0, 0, 0, 0, 0, 0, 0, 0,
2773 /* IP0_27_24 [4] */
2774 FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
2775 0, 0, 0, 0, 0, 0, 0, 0,
2776 /* IP0_23_20 [4] */
2777 FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
2778 0, 0, 0, 0, 0, 0, 0, 0,
2779 /* IP0_19_16 [4] */
2780 FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
2781 0, 0, 0, 0, 0, 0, 0, 0,
2782 /* IP0_15_12 [4] */
2783 FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
2784 0, 0, 0, 0, 0, 0, 0, 0,
2785 /* IP0_11_8 [4] */
2786 FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
2787 0, 0, 0, 0, 0, 0, 0, 0,
2788 /* IP0_7_4 [4] */
2789 FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
2790 0, 0, 0, 0, 0, 0, 0, 0,
2791 /* IP0_3_0 [4] */
2792 FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
2793 0, 0, 0, 0, 0, 0, 0, 0, ))
2795 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2796 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2798 /* IP1_31_28 [4] */
2799 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
2800 0, 0, 0, 0, 0, 0, 0, 0,
2801 /* IP1_27_24 [4] */
2802 FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
2803 0, 0, 0, 0, 0, 0, 0, 0,
2804 /* IP1_23_20 [4] */
2805 FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
2806 FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2807 /* IP1_19_16 [4] */
2808 FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
2809 FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2810 /* IP1_15_12 [4] */
2811 FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
2812 FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2813 /* IP1_11_8 [4] */
2814 FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
2815 FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2816 /* IP1_7_4 [4] */
2817 FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
2818 0, 0, 0, 0, 0, 0, 0, 0,
2819 /* IP1_3_0 [4] */
2820 FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
2821 0, 0, 0, 0, 0, 0, 0, 0, ))
2823 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2824 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2826 /* IP2_31_28 [4] */
2827 FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
2828 0, 0, 0, 0, 0, 0, 0,
2829 /* IP2_27_24 [4] */
2830 FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
2831 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2832 /* IP2_23_20 [4] */
2833 FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
2834 0, 0, 0, 0, 0, 0, 0,
2835 /* IP2_19_16 [4] */
2836 FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
2837 0, 0, 0, 0, 0, 0, 0,
2838 /* IP2_15_12 [4] */
2839 FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
2840 0, 0, 0, 0, 0, 0, 0, 0, 0,
2841 /* IP2_11_8 [4] */
2842 FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
2843 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2844 /* IP2_7_4 [4] */
2846 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2847 /* IP2_3_0 [4] */
2848 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
2849 0, 0, 0, 0, 0, 0, 0, 0, ))
2851 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2852 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2854 /* IP3_31_28 [4] */
2855 FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2856 0, 0,
2857 /* IP3_27_24 [4] */
2858 FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2859 0, 0,
2860 /* IP3_23_20 [4] */
2861 FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2862 0, 0,
2863 /* IP3_19_16 [4] */
2864 FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2865 0, 0, 0, 0,
2866 /* IP3_15_12 [4] */
2867 FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2868 0, 0, 0,
2869 /* IP3_11_8 [4] */
2870 FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2871 0, 0,
2872 /* IP3_7_4 [4] */
2873 FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
2874 FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2875 /* IP3_3_0 [4] */
2876 FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
2877 0, FN_AVB_AVTP_CAPTURE_A,
2878 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2880 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2881 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2883 /* IP4_31_28 [4] */
2884 FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
2885 0, 0, 0, 0, 0, 0, 0, 0,
2886 /* IP4_27_24 [4] */
2887 FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
2888 0, 0, 0, 0, 0, 0, 0, 0,
2889 /* IP4_23_20 [4] */
2890 FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
2891 0, 0, 0, 0, 0,
2892 /* IP4_19_16 [4] */
2893 FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
2894 FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2895 /* IP4_15_12 [4] */
2896 FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
2897 0, 0, 0, 0, 0, 0, 0, 0,
2898 /* IP4_11_8 [4] */
2899 FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
2900 0, 0, 0, 0, 0, 0, 0, 0,
2901 /* IP4_7_4 [4] */
2902 FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
2903 0, 0, 0, 0, 0, 0, 0, 0,
2904 /* IP4_3_0 [4] */
2905 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
2906 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2908 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2909 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2911 /* IP5_31_28 [4] */
2912 FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
2913 0, 0, 0, 0, 0, 0,
2914 /* IP5_27_24 [4] */
2915 FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
2916 0, 0, 0, 0, 0, 0, 0, 0, 0,
2917 /* IP5_23_20 [4] */
2918 FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
2919 0, 0, 0, 0, 0, 0,
2920 /* IP5_19_16 [4] */
2921 FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
2922 0, 0, 0, 0, 0, 0, 0, 0,
2923 /* IP5_15_12 [4] */
2924 FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
2925 0, 0, 0, 0, 0, 0,
2926 /* IP5_11_8 [4] */
2927 FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
2928 FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2929 /* IP5_7_4 [4] */
2930 FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
2931 0, 0, 0, 0, 0, 0, 0, 0,
2932 /* IP5_3_0 [4] */
2933 FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
2934 0, 0, 0, 0, 0, 0, 0, 0, ))
2936 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2937 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2939 /* IP6_31_28 [4] */
2940 FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
2941 0, 0, 0, 0, 0, 0, 0,
2942 /* IP6_27_24 [4] */
2943 FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
2944 FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2945 /* IP6_23_20 [4] */
2946 FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
2947 FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2948 /* IP6_19_16 [4] */
2949 FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
2950 0, 0, 0, 0, 0, 0,
2951 /* IP6_15_12 [4] */
2952 FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
2953 0, 0, 0, 0, 0, 0,
2954 /* IP6_11_8 [4] */
2955 FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
2956 0, 0, 0, 0, 0, 0, 0, 0, 0,
2957 /* IP6_7_4 [4] */
2958 FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
2959 0, 0, 0, 0, 0, 0, 0, 0, 0,
2960 /* IP6_3_0 [4] */
2961 FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
2962 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2964 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2965 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2967 /* IP7_31_28 [4] */
2968 FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
2969 0, 0, 0, 0, 0,
2970 /* IP7_27_24 [4] */
2971 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
2972 0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2973 /* IP7_23_20 [4] */
2974 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
2975 0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2976 /* IP7_19_16 [4] */
2977 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
2978 0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2979 /* IP7_15_12 [4] */
2980 FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
2981 FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2982 /* IP7_11_8 [4] */
2983 FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
2984 0, 0, 0, 0, 0,
2985 /* IP7_7_4 [4] */
2986 FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
2987 0, 0, 0, 0, 0, 0,
2988 /* IP7_3_0 [4] */
2989 FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
2990 0, 0, 0, 0, 0, 0, 0, ))
2992 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
2993 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2995 /* IP8_31_28 [4] */
2996 FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
2997 0, 0, 0, 0, 0, 0,
2998 /* IP8_27_24 [4] */
2999 FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
3000 0, 0, 0, 0, 0, 0,
3001 /* IP8_23_20 [4] */
3002 FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
3003 0, 0, 0, 0, 0, 0,
3004 /* IP8_19_16 [4] */
3005 FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
3006 0, 0, 0, 0, 0, 0,
3007 /* IP8_15_12 [4] */
3008 FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
3009 0, 0, 0, 0, 0, 0,
3010 /* IP8_11_8 [4] */
3011 FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
3012 0, 0, 0, 0, 0, 0, 0,
3013 /* IP8_7_4 [4] */
3014 FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
3015 0, 0, 0, 0, 0, 0, 0,
3016 /* IP8_3_0 [4] */
3017 FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
3018 0, 0, 0, 0, ))
3020 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
3021 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3023 /* IP9_31_28 [4] */
3024 FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
3025 0, 0, 0, 0, 0,
3026 /* IP9_27_24 [4] */
3027 FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
3028 0, 0, 0, 0, 0,
3029 /* IP9_23_20 [4] */
3031 FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3032 /* IP9_19_16 [4] */
3033 FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
3034 FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3035 /* IP9_15_12 [4] */
3036 FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
3037 0, 0, 0, 0, 0, 0, 0, 0, 0,
3038 /* IP9_11_8 [4] */
3039 FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
3040 0, 0, 0, 0, 0, 0, 0, 0, 0,
3041 /* IP9_7_4 [4] */
3042 FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
3043 0, 0, 0, 0, 0, 0,
3044 /* IP9_3_0 [4] */
3045 FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
3046 0, 0, 0, 0, 0, 0, ))
3048 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
3049 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3051 /* IP10_31_28 [4] */
3052 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
3053 FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
3054 /* IP10_27_24 [4] */
3056 FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3057 /* IP10_23_20 [4] */
3059 FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3060 /* IP10_19_16 [4] */
3061 FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
3062 FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
3063 0, 0,
3064 /* IP10_15_12 [4] */
3065 FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
3066 FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3067 /* IP10_11_8 [4] */
3068 FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
3069 FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3070 /* IP10_7_4 [4] */
3071 FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
3072 0, 0, 0, 0, 0, 0, 0,
3073 /* IP10_3_0 [4] */
3074 FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
3075 0, 0, 0, 0, 0, 0, 0, ))
3077 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
3078 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3080 /* IP11_31_28 [4] */
3081 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
3082 0, 0, 0, 0, 0, 0, 0, 0, 0,
3083 /* IP11_27_24 [4] */
3084 FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
3085 FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3086 /* IP11_23_20 [4] */
3087 FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
3088 FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3089 /* IP11_19_16 [4] */
3090 FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
3091 0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
3092 0, 0, 0, 0,
3093 /* IP11_15_12 [4] */
3094 FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
3095 0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
3096 0, 0, 0, 0, 0, 0, 0, 0,
3097 /* IP11_11_8 [4] */
3098 FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
3100 0, 0, 0, 0, 0, 0, 0, 0,
3101 /* IP11_7_4 [4] */
3102 FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
3104 0, 0, 0, 0, 0, 0, 0, 0,
3105 /* IP11_3_0 [4] */
3106 FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
3107 FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
3109 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
3110 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3112 /* IP12_31_28 [4] */
3113 FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
3114 0, 0, 0, 0, 0, 0, 0, 0, 0,
3115 /* IP12_27_24 [4] */
3117 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3118 /* IP12_23_20 [4] */
3120 FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3121 /* IP12_19_16 [4] */
3123 FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3124 /* IP12_15_12 [4] */
3125 FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
3126 0, 0, 0, 0, 0, 0, 0, 0,
3127 /* IP12_11_8 [4] */
3128 FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
3129 0, 0, 0, 0, 0, 0, 0, 0,
3130 /* IP12_7_4 [4] */
3131 FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
3132 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3133 /* IP12_3_0 [4] */
3134 FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
3135 0, 0, 0, 0, 0, 0, ))
3137 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
3138 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3140 /* IP13_31_28 [4] */
3141 FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
3142 0, 0, 0, 0, 0,
3143 /* IP13_27_24 [4] */
3144 FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
3145 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3146 /* IP13_23_20 [4] */
3147 FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
3148 FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3149 /* IP13_19_16 [4] */
3151 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3152 /* IP13_15_12 [4] */
3154 FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
3155 0, 0,
3156 /* IP13_11_8 [4] */
3157 FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
3158 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3159 /* IP13_7_4 [4] */
3160 FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
3161 0, 0, 0, 0, 0, 0, 0, 0, 0,
3162 /* IP13_3_0 [4] */
3163 FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
3164 0, 0, 0, 0, 0, 0, 0, 0, ))
3166 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
3167 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3169 /* IP14_31_28 [4] */
3170 FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
3171 FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3172 /* IP14_27_24 [4] */
3173 FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
3174 0, 0, 0, 0, 0,
3175 /* IP14_23_20 [4] */
3176 FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
3177 0, 0, 0, 0, 0, 0,
3178 /* IP14_19_16 [4] */
3179 FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
3180 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3181 /* IP14_15_12 [4] */
3182 FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
3183 0, 0, 0, 0, 0, 0, 0, 0, 0,
3184 /* IP14_11_8 [4] */
3185 FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
3186 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3187 /* IP14_7_4 [4] */
3188 FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
3189 0, 0, 0, 0, 0, 0, 0, 0, 0,
3190 /* IP14_3_0 [4] */
3191 FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
3192 0, 0, 0, 0, 0, 0, ))
3194 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
3195 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3197 /* IP15_31_28 [4] */
3198 FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
3199 0, 0, 0, 0, 0, 0,
3200 /* IP15_27_24 [4] */
3201 FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
3202 0, 0, 0, 0, 0, 0,
3203 /* IP15_23_20 [4] */
3204 FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
3205 FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3206 /* IP15_19_16 [4] */
3207 FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
3208 FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3209 /* IP15_15_12 [4] */
3210 FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
3211 FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3212 /* IP15_11_8 [4] */
3213 FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
3214 FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3215 /* IP15_7_4 [4] */
3216 FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
3217 FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3218 /* IP15_3_0 [4] */
3219 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
3220 FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3222 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
3223 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3225 /* IP16_31_28 [4] */
3226 FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
3227 FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3228 /* IP16_27_24 [4] */
3229 FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
3230 FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3231 /* IP16_23_20 [4] */
3232 FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
3233 FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3234 /* IP16_19_16 [4] */
3235 FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
3236 0, 0, 0, 0, 0, 0, 0, 0, 0,
3237 /* IP16_15_12 [4] */
3238 FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
3239 FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
3240 0, 0, 0,
3241 /* IP16_11_8 [4] */
3242 FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
3243 FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3244 /* IP16_7_4 [4] */
3246 FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
3247 /* IP16_3_0 [4] */
3248 FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
3249 0, 0, 0, 0, 0, 0, ))
3251 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
3252 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3254 /* IP17_31_28 [4] */
3255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3256 /* IP17_27_24 [4] */
3257 FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
3258 FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3259 /* IP17_23_20 [4] */
3260 FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
3261 FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3262 /* IP17_19_16 [4] */
3263 FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
3264 FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3265 /* IP17_15_12 [4] */
3266 FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
3267 FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3268 /* IP17_11_8 [4] */
3269 FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
3270 FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3271 /* IP17_7_4 [4] */
3272 FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
3273 FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3274 /* IP17_3_0 [4] */
3275 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
3276 FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3278 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
3283 0, 0,
3285 0, 0,
3287 0, 0,
3289 0, 0,
3291 0, 0,
3295 0, 0,
3297 0, 0,
3306 0, 0,
3309 FN_SEL_I2C04_4, 0, 0, 0,
3312 FN_SEL_I2C03_4, 0, 0, 0,
3314 0, 0,
3319 FN_SEL_I2C01_4, 0, 0, 0,
3322 FN_SEL_I2C00_4, 0, 0, 0,
3326 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
3334 FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
3337 FN_SEL_SCIF4_4, 0, 0, 0,
3339 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
3341 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
3349 FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
3351 0, 0,
3355 0, 0,
3361 0, 0, 0, 0,
3367 0, 0, 0, 0,
3369 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
3373 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
3378 0, 0,
3380 0, 0,
3382 0, 0,
3384 0, 0,
3386 0, 0,
3388 0, 0,
3390 0, 0,
3392 0, 0,
3394 0, 0,
3396 0, 0,
3398 FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
3400 FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
3402 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
3404 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
3406 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
3408 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
3410 FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
3412 FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
3414 FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
3418 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
3426 int bit = -EINVAL; in r8a77470_pin_to_pocctrl()
3428 *pocctrl = 0xe60600b0; in r8a77470_pin_to_pocctrl()
3430 if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10)) in r8a77470_pin_to_pocctrl()
3431 bit = 0; in r8a77470_pin_to_pocctrl()
3433 if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22)) in r8a77470_pin_to_pocctrl()
3436 if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19)) in r8a77470_pin_to_pocctrl()
3443 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
3444 /* PUPR0 pull-up pins */
3445 [ 0] = RCAR_GP_PIN(1, 0), /* D0 */
3446 [ 1] = RCAR_GP_PIN(0, 22), /* MMC0_D7 */
3447 [ 2] = RCAR_GP_PIN(0, 21), /* MMC0_D6 */
3448 [ 3] = RCAR_GP_PIN(0, 20), /* MMC0_D5 */
3449 [ 4] = RCAR_GP_PIN(0, 19), /* MMC0_D4 */
3450 [ 5] = RCAR_GP_PIN(0, 18), /* MMC0_D3 */
3451 [ 6] = RCAR_GP_PIN(0, 17), /* MMC0_D2 */
3452 [ 7] = RCAR_GP_PIN(0, 16), /* MMC0_D1 */
3453 [ 8] = RCAR_GP_PIN(0, 15), /* MMC0_D0 */
3454 [ 9] = RCAR_GP_PIN(0, 14), /* MMC0_CMD */
3455 [10] = RCAR_GP_PIN(0, 13), /* MMC0_CLK */
3456 [11] = RCAR_GP_PIN(0, 12), /* SD0_WP */
3457 [12] = RCAR_GP_PIN(0, 11), /* SD0_CD */
3458 [13] = RCAR_GP_PIN(0, 10), /* SD0_DAT3 */
3459 [14] = RCAR_GP_PIN(0, 9), /* SD0_DAT2 */
3460 [15] = RCAR_GP_PIN(0, 8), /* SD0_DAT1 */
3461 [16] = RCAR_GP_PIN(0, 7), /* SD0_DAT0 */
3462 [17] = RCAR_GP_PIN(0, 6), /* SD0_CMD */
3463 [18] = RCAR_GP_PIN(0, 5), /* SD0_CLK */
3464 [19] = RCAR_GP_PIN(0, 4), /* CLKOUT */
3466 [21] = RCAR_GP_PIN(0, 3), /* USB1_OVC */
3467 [22] = RCAR_GP_PIN(0, 2), /* USB1_PWEN */
3468 [23] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
3469 [24] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
3478 { PINMUX_BIAS_REG("N/A", 0, "PUPR0", 0xe6060100) {
3479 /* PUPR0 pull-down pins */
3480 [ 0] = SH_PFC_PIN_NONE,
3484 [ 4] = SH_PFC_PIN_NONE,
3513 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
3514 [ 0] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */
3518 [ 4] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */
3519 [ 5] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */
3523 [ 9] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */
3542 [28] = RCAR_GP_PIN(1, 4), /* D4 */
3547 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
3548 [ 0] = RCAR_GP_PIN(3, 9), /* VI1_CLKENB */
3552 [ 4] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */
3553 [ 5] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */
3557 [ 9] = RCAR_GP_PIN(3, 0), /* VI1_CLK */
3581 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
3582 [ 0] = RCAR_GP_PIN(4, 21), /* SD2_WP */
3583 [ 1] = RCAR_GP_PIN(4, 20), /* SD2_CD */
3584 [ 2] = RCAR_GP_PIN(4, 19), /* SD2_DAT3 */
3585 [ 3] = RCAR_GP_PIN(4, 18), /* SD2_DAT2 */
3586 [ 4] = RCAR_GP_PIN(4, 17), /* SD2_DAT1 */
3587 [ 5] = RCAR_GP_PIN(4, 16), /* SD2_DAT0 */
3588 [ 6] = RCAR_GP_PIN(4, 15), /* SD2_CMD */
3589 [ 7] = RCAR_GP_PIN(4, 14), /* SD2_CLK */
3590 [ 8] = RCAR_GP_PIN(4, 13), /* HRTS1#_A */
3591 [ 9] = RCAR_GP_PIN(4, 12), /* HCTS1#_A */
3592 [10] = RCAR_GP_PIN(4, 11), /* HTX1_A */
3593 [11] = RCAR_GP_PIN(4, 10), /* HRX1_A */
3594 [12] = RCAR_GP_PIN(4, 9), /* MSIOF0_SS2_A */
3595 [13] = RCAR_GP_PIN(4, 8), /* MSIOF0_SS1_A */
3596 [14] = RCAR_GP_PIN(4, 7), /* MSIOF0_SYNC_A */
3597 [15] = RCAR_GP_PIN(4, 6), /* MSIOF0_SCK_A */
3598 [16] = RCAR_GP_PIN(4, 5), /* MSIOF0_TXD_A */
3599 [17] = RCAR_GP_PIN(4, 4), /* MSIOF0_RXD_A */
3600 [18] = RCAR_GP_PIN(4, 3), /* SDA1_A */
3601 [19] = RCAR_GP_PIN(4, 2), /* SCL1_A */
3602 [20] = RCAR_GP_PIN(4, 1), /* SDA0_A */
3603 [21] = RCAR_GP_PIN(4, 0), /* SCL0_A */
3615 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
3616 [ 0] = RCAR_GP_PIN(5, 27), /* SSI_SDATA9_A */
3620 [ 4] = RCAR_GP_PIN(5, 23), /* SSI_WS2_A */
3639 [23] = RCAR_GP_PIN(5, 4), /* SSI_WS6_A */
3643 [27] = RCAR_GP_PIN(5, 0), /* SSI_SCK5_A */
3644 [28] = RCAR_GP_PIN(4, 25), /* SDA2_A */
3645 [29] = RCAR_GP_PIN(4, 24), /* SCL2_A */
3646 [30] = RCAR_GP_PIN(4, 23), /* TX3_A */
3647 [31] = RCAR_GP_PIN(4, 22), /* RX3_A */
3649 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
3650 [ 0] = SH_PFC_PIN_NONE,
3654 [ 4] = SH_PFC_PIN_NONE,
3696 .unlock_reg = 0xe6060000, /* PMMR */