Lines Matching full:pctrl
41 * @pctrl: pinctrl handle.
61 struct pinctrl_dev *pctrl; member
84 static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
89 static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
101 static void msm_ack_intr_status(struct msm_pinctrl *pctrl, in MSM_ACCESSOR()
106 msm_writel_intr_status(val, pctrl, g); in MSM_ACCESSOR()
111 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_groups_count() local
113 return pctrl->soc->ngroups; in msm_get_groups_count()
119 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_name() local
121 return pctrl->soc->groups[group].name; in msm_get_group_name()
129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_group_pins() local
131 *pins = pctrl->soc->groups[group].pins; in msm_get_group_pins()
132 *num_pins = pctrl->soc->groups[group].npins; in msm_get_group_pins()
146 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request() local
147 struct gpio_chip *chip = &pctrl->chip; in msm_pinmux_request()
154 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_functions_count() local
156 return pctrl->soc->nfunctions; in msm_get_functions_count()
162 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_name() local
164 return pctrl->soc->functions[function].name; in msm_get_function_name()
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_get_function_groups() local
174 *groups = pctrl->soc->functions[function].groups; in msm_get_function_groups()
175 *num_groups = pctrl->soc->functions[function].ngroups; in msm_get_function_groups()
183 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_set_mux() local
184 struct gpio_chip *gc = &pctrl->chip; in msm_pinmux_set_mux()
187 unsigned int gpio_func = pctrl->soc->gpio_func; in msm_pinmux_set_mux()
193 g = &pctrl->soc->groups[group]; in msm_pinmux_set_mux()
215 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) in msm_pinmux_set_mux()
218 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_pinmux_set_mux()
220 val = msm_readl_ctl(pctrl, g); in msm_pinmux_set_mux()
223 msm_writel_ctl(val, pctrl, g); in msm_pinmux_set_mux()
225 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_pinmux_set_mux()
228 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { in msm_pinmux_set_mux()
233 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_pinmux_set_mux()
236 msm_ack_intr_status(pctrl, g); in msm_pinmux_set_mux()
248 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_pinmux_request_gpio() local
249 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; in msm_pinmux_request_gpio()
255 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); in msm_pinmux_request_gpio()
267 static int msm_config_reg(struct msm_pinctrl *pctrl, in msm_config_reg() argument
317 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_get() local
325 g = &pctrl->soc->groups[group]; in msm_config_group_get()
327 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_get()
331 val = msm_readl_ctl(pctrl, g); in msm_config_group_get()
347 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
355 if (pctrl->soc->pull_no_keeper) in msm_config_group_get()
376 val = msm_readl_io(pctrl, g); in msm_config_group_get()
400 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); in msm_config_group_set() local
410 g = &pctrl->soc->groups[group]; in msm_config_group_set()
416 ret = msm_config_reg(pctrl, g, param, &mask, &bit); in msm_config_group_set()
429 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
435 if (pctrl->soc->pull_no_keeper) in msm_config_group_set()
452 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
453 val = msm_readl_io(pctrl, g); in msm_config_group_set()
458 msm_writel_io(val, pctrl, g); in msm_config_group_set()
459 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
469 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", in msm_config_group_set()
476 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); in msm_config_group_set()
480 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_config_group_set()
481 val = msm_readl_ctl(pctrl, g); in msm_config_group_set()
484 msm_writel_ctl(val, pctrl, g); in msm_config_group_set()
485 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_config_group_set()
500 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_input() local
504 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_input()
506 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_input()
508 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_input()
510 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_input()
512 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_input()
520 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_direction_output() local
524 g = &pctrl->soc->groups[offset]; in msm_gpio_direction_output()
526 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_direction_output()
528 val = msm_readl_io(pctrl, g); in msm_gpio_direction_output()
533 msm_writel_io(val, pctrl, g); in msm_gpio_direction_output()
535 val = msm_readl_ctl(pctrl, g); in msm_gpio_direction_output()
537 msm_writel_ctl(val, pctrl, g); in msm_gpio_direction_output()
539 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_direction_output()
546 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get_direction() local
550 g = &pctrl->soc->groups[offset]; in msm_gpio_get_direction()
552 val = msm_readl_ctl(pctrl, g); in msm_gpio_get_direction()
561 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_get() local
564 g = &pctrl->soc->groups[offset]; in msm_gpio_get()
566 val = msm_readl_io(pctrl, g); in msm_gpio_get()
573 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_set() local
577 g = &pctrl->soc->groups[offset]; in msm_gpio_set()
579 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_set()
581 val = msm_readl_io(pctrl, g); in msm_gpio_set()
586 msm_writel_io(val, pctrl, g); in msm_gpio_set()
588 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_set()
601 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); in msm_gpio_dbg_show_one() local
625 g = &pctrl->soc->groups[offset]; in msm_gpio_dbg_show_one()
626 ctl_reg = msm_readl_ctl(pctrl, g); in msm_gpio_dbg_show_one()
627 io_reg = msm_readl_io(pctrl, g); in msm_gpio_dbg_show_one()
642 if (pctrl->soc->pull_no_keeper) in msm_gpio_dbg_show_one()
666 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_init_valid_mask() local
669 const int *reserved = pctrl->soc->reserved_gpios; in msm_gpio_init_valid_mask()
677 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); in msm_gpio_init_valid_mask()
687 len = ret = device_property_count_u16(pctrl->dev, "gpios"); in msm_gpio_init_valid_mask()
698 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); in msm_gpio_init_valid_mask()
700 dev_err(pctrl->dev, "could not read list of GPIOs\n"); in msm_gpio_init_valid_mask()
744 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, in msm_gpio_update_dual_edge_pos() argument
753 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
755 pol = msm_readl_intr_cfg(pctrl, g); in msm_gpio_update_dual_edge_pos()
757 msm_writel_intr_cfg(pol, pctrl, g); in msm_gpio_update_dual_edge_pos()
759 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_pos()
760 intstat = msm_readl_intr_status(pctrl, g); in msm_gpio_update_dual_edge_pos()
764 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", in msm_gpio_update_dual_edge_pos()
771 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_mask() local
779 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_mask()
782 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_mask()
784 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_mask()
786 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_mask()
811 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_mask()
813 clear_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_mask()
815 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_mask()
821 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_unmask() local
829 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_unmask()
832 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_unmask()
834 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_unmask()
836 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_unmask()
839 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_unmask()
841 set_bit(d->hwirq, pctrl->enabled_irqs); in msm_gpio_irq_unmask()
843 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_unmask()
849 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_enable() local
854 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_enable()
861 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_disable() local
866 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_disable()
882 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_update_dual_edge_parent() local
883 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_update_dual_edge_parent()
889 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
902 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); in msm_gpio_update_dual_edge_parent()
913 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); in msm_gpio_update_dual_edge_parent()
919 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_ack() local
923 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_ack()
924 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
929 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_ack()
931 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_ack()
933 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_ack()
935 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_ack()
936 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_ack()
938 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_ack()
945 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_needs_dual_edge_parent_workaround() local
948 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && in msm_gpio_needs_dual_edge_parent_workaround()
949 test_bit(d->hwirq, pctrl->skip_wake_irqs); in msm_gpio_needs_dual_edge_parent_workaround()
955 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_type() local
962 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
971 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { in msm_gpio_irq_set_type()
972 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
977 g = &pctrl->soc->groups[d->hwirq]; in msm_gpio_irq_set_type()
979 raw_spin_lock_irqsave(&pctrl->lock, flags); in msm_gpio_irq_set_type()
985 set_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
987 clear_bit(d->hwirq, pctrl->dual_edge_irqs); in msm_gpio_irq_set_type()
993 if (pctrl->intr_target_use_scm) { in msm_gpio_irq_set_type()
994 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; in msm_gpio_irq_set_type()
1004 dev_err(pctrl->dev, in msm_gpio_irq_set_type()
1008 val = msm_readl_intr_target(pctrl, g); in msm_gpio_irq_set_type()
1011 msm_writel_intr_target(val, pctrl, g); in msm_gpio_irq_set_type()
1019 val = msm_readl_intr_cfg(pctrl, g); in msm_gpio_irq_set_type()
1068 msm_writel_intr_cfg(val, pctrl, g); in msm_gpio_irq_set_type()
1076 msm_ack_intr_status(pctrl, g); in msm_gpio_irq_set_type()
1078 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) in msm_gpio_irq_set_type()
1079 msm_gpio_update_dual_edge_pos(pctrl, g, d); in msm_gpio_irq_set_type()
1081 raw_spin_unlock_irqrestore(&pctrl->lock, flags); in msm_gpio_irq_set_type()
1094 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_wake() local
1102 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_wake()
1105 return irq_set_irq_wake(pctrl->irq, on); in msm_gpio_irq_set_wake()
1111 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_reqres() local
1117 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); in msm_gpio_irq_reqres()
1155 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_affinity() local
1157 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_affinity()
1166 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_set_vcpu_affinity() local
1168 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) in msm_gpio_irq_set_vcpu_affinity()
1178 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_irq_handler() local
1190 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { in msm_gpio_irq_handler()
1191 g = &pctrl->soc->groups[i]; in msm_gpio_irq_handler()
1192 val = msm_readl_intr_status(pctrl, g); in msm_gpio_irq_handler()
1212 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); in msm_gpio_wakeirq() local
1219 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_wakeirq()
1220 map = &pctrl->soc->wakeirq_map[i]; in msm_gpio_wakeirq()
1230 static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) in msm_gpio_needs_valid_mask() argument
1232 if (pctrl->soc->reserved_gpios) in msm_gpio_needs_valid_mask()
1235 return device_property_count_u16(pctrl->dev, "gpios") > 0; in msm_gpio_needs_valid_mask()
1238 static int msm_gpio_init(struct msm_pinctrl *pctrl) in msm_gpio_init() argument
1243 unsigned gpio, ngpio = pctrl->soc->ngpios; in msm_gpio_init()
1250 chip = &pctrl->chip; in msm_gpio_init()
1253 chip->label = dev_name(pctrl->dev); in msm_gpio_init()
1254 chip->parent = pctrl->dev; in msm_gpio_init()
1256 chip->of_node = pctrl->dev->of_node; in msm_gpio_init()
1257 if (msm_gpio_needs_valid_mask(pctrl)) in msm_gpio_init()
1260 pctrl->irq_chip.name = "msmgpio"; in msm_gpio_init()
1261 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable; in msm_gpio_init()
1262 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable; in msm_gpio_init()
1263 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask; in msm_gpio_init()
1264 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask; in msm_gpio_init()
1265 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack; in msm_gpio_init()
1266 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type; in msm_gpio_init()
1267 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake; in msm_gpio_init()
1268 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; in msm_gpio_init()
1269 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; in msm_gpio_init()
1270 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity; in msm_gpio_init()
1271 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity; in msm_gpio_init()
1272 pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND | in msm_gpio_init()
1276 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); in msm_gpio_init()
1284 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent; in msm_gpio_init()
1290 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { in msm_gpio_init()
1291 gpio = pctrl->soc->wakeirq_map[i].gpio; in msm_gpio_init()
1292 set_bit(gpio, pctrl->skip_wake_irqs); in msm_gpio_init()
1297 girq->chip = &pctrl->irq_chip; in msm_gpio_init()
1299 girq->fwnode = pctrl->dev->fwnode; in msm_gpio_init()
1301 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), in msm_gpio_init()
1307 girq->parents[0] = pctrl->irq; in msm_gpio_init()
1309 ret = gpiochip_add_data(&pctrl->chip, pctrl); in msm_gpio_init()
1311 dev_err(pctrl->dev, "Failed register gpiochip\n"); in msm_gpio_init()
1325 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { in msm_gpio_init()
1326 ret = gpiochip_add_pin_range(&pctrl->chip, in msm_gpio_init()
1327 dev_name(pctrl->dev), 0, 0, chip->ngpio); in msm_gpio_init()
1329 dev_err(pctrl->dev, "Failed to add pin range\n"); in msm_gpio_init()
1330 gpiochip_remove(&pctrl->chip); in msm_gpio_init()
1341 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); in msm_ps_hold_restart() local
1343 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); in msm_ps_hold_restart()
1355 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) in msm_pinctrl_setup_pm_reset() argument
1358 const struct msm_function *func = pctrl->soc->functions; in msm_pinctrl_setup_pm_reset()
1360 for (i = 0; i < pctrl->soc->nfunctions; i++) in msm_pinctrl_setup_pm_reset()
1362 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; in msm_pinctrl_setup_pm_reset()
1363 pctrl->restart_nb.priority = 128; in msm_pinctrl_setup_pm_reset()
1364 if (register_restart_handler(&pctrl->restart_nb)) in msm_pinctrl_setup_pm_reset()
1365 dev_err(pctrl->dev, in msm_pinctrl_setup_pm_reset()
1367 poweroff_pctrl = pctrl; in msm_pinctrl_setup_pm_reset()
1375 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_suspend() local
1377 return pinctrl_force_sleep(pctrl->pctrl); in msm_pinctrl_suspend()
1382 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); in msm_pinctrl_resume() local
1384 return pinctrl_force_default(pctrl->pctrl); in msm_pinctrl_resume()
1395 struct msm_pinctrl *pctrl; in msm_pinctrl_probe() local
1400 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); in msm_pinctrl_probe()
1401 if (!pctrl) in msm_pinctrl_probe()
1404 pctrl->dev = &pdev->dev; in msm_pinctrl_probe()
1405 pctrl->soc = soc_data; in msm_pinctrl_probe()
1406 pctrl->chip = msm_gpio_template; in msm_pinctrl_probe()
1407 pctrl->intr_target_use_scm = of_device_is_compatible( in msm_pinctrl_probe()
1408 pctrl->dev->of_node, in msm_pinctrl_probe()
1411 raw_spin_lock_init(&pctrl->lock); in msm_pinctrl_probe()
1417 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1418 if (IS_ERR(pctrl->regs[i])) in msm_pinctrl_probe()
1419 return PTR_ERR(pctrl->regs[i]); in msm_pinctrl_probe()
1423 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res); in msm_pinctrl_probe()
1424 if (IS_ERR(pctrl->regs[0])) in msm_pinctrl_probe()
1425 return PTR_ERR(pctrl->regs[0]); in msm_pinctrl_probe()
1427 pctrl->phys_base[0] = res->start; in msm_pinctrl_probe()
1430 msm_pinctrl_setup_pm_reset(pctrl); in msm_pinctrl_probe()
1432 pctrl->irq = platform_get_irq(pdev, 0); in msm_pinctrl_probe()
1433 if (pctrl->irq < 0) in msm_pinctrl_probe()
1434 return pctrl->irq; in msm_pinctrl_probe()
1436 pctrl->desc.owner = THIS_MODULE; in msm_pinctrl_probe()
1437 pctrl->desc.pctlops = &msm_pinctrl_ops; in msm_pinctrl_probe()
1438 pctrl->desc.pmxops = &msm_pinmux_ops; in msm_pinctrl_probe()
1439 pctrl->desc.confops = &msm_pinconf_ops; in msm_pinctrl_probe()
1440 pctrl->desc.name = dev_name(&pdev->dev); in msm_pinctrl_probe()
1441 pctrl->desc.pins = pctrl->soc->pins; in msm_pinctrl_probe()
1442 pctrl->desc.npins = pctrl->soc->npins; in msm_pinctrl_probe()
1444 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); in msm_pinctrl_probe()
1445 if (IS_ERR(pctrl->pctrl)) { in msm_pinctrl_probe()
1447 return PTR_ERR(pctrl->pctrl); in msm_pinctrl_probe()
1450 ret = msm_gpio_init(pctrl); in msm_pinctrl_probe()
1454 platform_set_drvdata(pdev, pctrl); in msm_pinctrl_probe()
1464 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); in msm_pinctrl_remove() local
1466 gpiochip_remove(&pctrl->chip); in msm_pinctrl_remove()
1468 unregister_restart_handler(&pctrl->restart_nb); in msm_pinctrl_remove()