1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinmux.h>
22 #include "../pinctrl-utils.h"
42 #define LPI_GPIO_DS_TO_VAL(v)		(v / 2 - 1)
43 #define NO_SLEW				-1
109 /* sm8250 variant specific data */
242 	return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);  in lpi_gpio_read()
248 	iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);  in lpi_gpio_write()
257 	return pctrl->data->ngroups;  in lpi_gpio_get_groups_count()
265 	return pctrl->data->groups[group].name;  in lpi_gpio_get_group_name()
275 	*pins = pctrl->data->groups[group].pins;  in lpi_gpio_get_group_pins()
276 	*num_pins = pctrl->data->groups[group].npins;  in lpi_gpio_get_group_pins()
293 	return pctrl->data->nfunctions;  in lpi_gpio_get_functions_count()
301 	return pctrl->data->functions[function].name;  in lpi_gpio_get_function_name()
311 	*groups = pctrl->data->functions[function].groups;  in lpi_gpio_get_function_groups()
312 	*num_qgroups = pctrl->data->functions[function].ngroups;  in lpi_gpio_get_function_groups()
321 	const struct lpi_pingroup *g = &pctrl->data->groups[group_num];  in lpi_gpio_set_mux()
323 	int i, pin = g->pin;  in lpi_gpio_set_mux()
325 	for (i = 0; i < g->nfuncs; i++) {  in lpi_gpio_set_mux()
326 		if (g->funcs[i] == function)  in lpi_gpio_set_mux()
330 	if (WARN_ON(i == g->nfuncs))  in lpi_gpio_set_mux()
331 		return -EINVAL;  in lpi_gpio_set_mux()
351 	struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);  in lpi_config_get()
384 		return -EINVAL;  in lpi_config_get()
394 	struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);  in lpi_config_set()
402 	g = &pctrl->data->groups[group];  in lpi_config_set()
432 				dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",  in lpi_config_set()
434 				return -EINVAL;  in lpi_config_set()
437 			slew_offset = g->slew_offset;  in lpi_config_set()
441 			mutex_lock(&pctrl->slew_access_lock);  in lpi_config_set()
443 			sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);  in lpi_config_set()
446 			iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);  in lpi_config_set()
448 			mutex_unlock(&pctrl->slew_access_lock);  in lpi_config_set()
451 			return -EINVAL;  in lpi_config_set()
485 	return lpi_config_set(state->ctrl, pin, &config, 1);  in lpi_gpio_direction_input()
496 	return lpi_config_set(state->ctrl, pin, &config, 1);  in lpi_gpio_direction_output()
514 	lpi_config_set(state->ctrl, pin, &config, 1);  in lpi_gpio_set()
546 	pctldev = pctldev ? : state->ctrl;  in lpi_gpio_dbg_show_one()
547 	pindesc = pctldev->desc->pins[offset];  in lpi_gpio_dbg_show_one()
555 	seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);  in lpi_gpio_dbg_show_one()
562 	unsigned int gpio = chip->base;  in lpi_gpio_dbg_show()
565 	for (i = 0; i < chip->ngpio; i++, gpio++) {  in lpi_gpio_dbg_show()
588 	struct device *dev = &pdev->dev;  in lpi_pinctrl_probe()
594 		return -ENOMEM;  in lpi_pinctrl_probe()
600 		return -EINVAL;  in lpi_pinctrl_probe()
602 	pctrl->data = data;  in lpi_pinctrl_probe()
603 	pctrl->dev = &pdev->dev;  in lpi_pinctrl_probe()
605 	pctrl->clks[0].id = "core";  in lpi_pinctrl_probe()
606 	pctrl->clks[1].id = "audio";  in lpi_pinctrl_probe()
608 	pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);  in lpi_pinctrl_probe()
609 	if (IS_ERR(pctrl->tlmm_base))  in lpi_pinctrl_probe()
610 		return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),  in lpi_pinctrl_probe()
613 	pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);  in lpi_pinctrl_probe()
614 	if (IS_ERR(pctrl->slew_base))  in lpi_pinctrl_probe()
615 		return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),  in lpi_pinctrl_probe()
618 	ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);  in lpi_pinctrl_probe()
622 	ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);  in lpi_pinctrl_probe()
626 	pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;  in lpi_pinctrl_probe()
627 	pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;  in lpi_pinctrl_probe()
628 	pctrl->desc.confops = &lpi_gpio_pinconf_ops;  in lpi_pinctrl_probe()
629 	pctrl->desc.owner = THIS_MODULE;  in lpi_pinctrl_probe()
630 	pctrl->desc.name = dev_name(dev);  in lpi_pinctrl_probe()
631 	pctrl->desc.pins = data->pins;  in lpi_pinctrl_probe()
632 	pctrl->desc.npins = data->npins;  in lpi_pinctrl_probe()
633 	pctrl->chip = lpi_gpio_template;  in lpi_pinctrl_probe()
634 	pctrl->chip.parent = dev;  in lpi_pinctrl_probe()
635 	pctrl->chip.base = -1;  in lpi_pinctrl_probe()
636 	pctrl->chip.ngpio = data->npins;  in lpi_pinctrl_probe()
637 	pctrl->chip.label = dev_name(dev);  in lpi_pinctrl_probe()
638 	pctrl->chip.of_gpio_n_cells = 2;  in lpi_pinctrl_probe()
639 	pctrl->chip.can_sleep = false;  in lpi_pinctrl_probe()
641 	mutex_init(&pctrl->slew_access_lock);  in lpi_pinctrl_probe()
643 	pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);  in lpi_pinctrl_probe()
644 	if (IS_ERR(pctrl->ctrl)) {  in lpi_pinctrl_probe()
645 		ret = PTR_ERR(pctrl->ctrl);  in lpi_pinctrl_probe()
650 	ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);  in lpi_pinctrl_probe()
652 		dev_err(pctrl->dev, "can't add gpio chip\n");  in lpi_pinctrl_probe()
659 	mutex_destroy(&pctrl->slew_access_lock);  in lpi_pinctrl_probe()
660 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);  in lpi_pinctrl_probe()
669 	mutex_destroy(&pctrl->slew_access_lock);  in lpi_pinctrl_remove()
670 	clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);  in lpi_pinctrl_remove()
677 	       .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
686 		   .name = "qcom-lpass-lpi-pinctrl",
694 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");