Lines Matching +full:jz4780 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/pinctrl/pinconf-generic.h>
175 INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
176 INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
177 INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
178 INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
179 INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
180 INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
181 INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
182 INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
183 INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
184 INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
185 INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
186 INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
187 INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
188 INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
189 INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
190 INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
195 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
196 static const char *jz4730_uart0_groups[] = { "uart0-data", };
197 static const char *jz4730_uart1_groups[] = { "uart1-data", };
198 static const char *jz4730_uart2_groups[] = { "uart2-data", };
199 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
201 "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
204 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
271 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
272 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
273 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
274 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
275 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
276 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
277 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
278 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
279 INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
280 INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
281 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
282 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
283 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
284 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
285 INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
296 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
297 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
298 static const char *jz4740_uart1_groups[] = { "uart1-data", };
300 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
303 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
374 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
375 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
377 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
378 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
379 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
380 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
381 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
382 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
383 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
384 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
385 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
386 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
387 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
388 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
389 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
390 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
391 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
400 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
401 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
402 static const char *jz4725b_uart_groups[] = { "uart-data", };
404 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
405 "lcd-special", "lcd-generic",
408 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
409 "nand-cle-ale", "nand-fre-fwe",
493 INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
494 INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
495 INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
496 INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
497 INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
498 INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
499 INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
500 INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
501 INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
502 INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
503 INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
504 INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
505 INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
506 INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
507 INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
508 INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
509 INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
510 INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
511 INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
512 INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
513 INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
514 INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
515 INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
516 INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
517 INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
526 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
527 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
528 static const char *jz4750_uart2_groups[] = { "uart2-data", };
529 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
531 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
533 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
534 static const char *jz4750_i2c_groups[] = { "i2c-data", };
535 static const char *jz4750_cim_groups[] = { "cim-data", };
537 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
538 "lcd-special", "lcd-generic",
541 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
557 { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), },
642 INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
643 INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
644 INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),
645 INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
646 INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
647 INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
648 INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
649 INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
650 INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
651 INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
652 INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
653 INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
654 INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
655 INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
656 INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
657 INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
658 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
660 INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
662 INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
663 INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
664 INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
665 INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
666 INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
667 INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
668 INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
669 INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
671 INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
672 INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
673 INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
674 INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
675 INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
676 INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
677 INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
686 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
687 static const char *jz4755_uart1_groups[] = { "uart1-data", };
688 static const char *jz4755_uart2_groups[] = { "uart2-data", };
690 "ssi-dt-b", "ssi-dt-f",
691 "ssi-dr-b", "ssi-dr-f",
692 "ssi-clk-b", "ssi-clk-f",
693 "ssi-gpc-b", "ssi-gpc-f",
694 "ssi-ce0-b", "ssi-ce0-f",
695 "ssi-ce1-b", "ssi-ce1-f",
697 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
698 static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
699 static const char *jz4755_i2c_groups[] = { "i2c-data", };
700 static const char *jz4755_cim_groups[] = { "cim-data", };
702 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
703 "lcd-special", "lcd-generic",
706 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
722 { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
881 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
882 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
883 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
884 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
885 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
886 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
887 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
889 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
890 INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
891 INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
892 INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
893 INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
894 INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
895 INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
896 INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
897 INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
898 INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
899 INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
900 INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
901 INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
902 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
903 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
904 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
905 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
906 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
907 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
908 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
909 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
910 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
911 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
912 INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
913 INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
914 INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
915 INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
916 INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
917 INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
918 INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
919 INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
920 INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
921 INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
922 INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
923 INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
924 INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
925 INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
926 INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
927 INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
928 INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
929 INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
930 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
931 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
932 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
933 INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
934 INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
935 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
936 INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
937 INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
938 INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
939 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
940 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
941 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
942 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
944 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
945 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
946 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
947 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
948 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
949 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
950 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
951 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
952 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
953 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
954 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
955 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
956 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
957 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
958 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
959 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
960 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
961 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
962 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
963 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
964 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
965 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
966 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
967 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
968 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
969 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
970 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
971 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
972 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
973 INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
974 INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
975 INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
976 INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
977 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
978 INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
979 INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
988 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
991 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
992 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
993 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
994 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
996 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
997 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
998 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
999 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1000 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1001 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1004 "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1005 "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1006 "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1007 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1008 "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1009 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1012 "mmc0-1bit-a", "mmc0-4bit-a",
1013 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1016 "mmc1-1bit-d", "mmc1-4bit-d",
1017 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1020 "mmc2-1bit-b", "mmc2-4bit-b",
1021 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1024 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1025 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1027 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1028 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1029 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1030 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1031 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1032 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1033 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1034 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1035 static const char *jz4760_cim_groups[] = { "cim-data", };
1037 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1038 "lcd-special", "lcd-generic",
1048 static const char *jz4760_otg_groups[] = { "otg-vbus", };
1061 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
1062 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
1063 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
1064 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
1065 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
1066 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
1226 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1227 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1228 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1229 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1230 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1231 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1232 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1234 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1235 INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1236 INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1237 INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1238 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1239 INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1240 INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1241 INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1242 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1243 INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1244 INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1245 INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1246 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1247 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1248 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1249 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1250 INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1251 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1252 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1253 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1254 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1255 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1256 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1257 INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1258 INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1259 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1260 INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1261 INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1262 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1263 INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1264 INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1265 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1266 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1267 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1268 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1269 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1270 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1271 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1272 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1273 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1274 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1275 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1277 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1278 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1279 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1280 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1281 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1282 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1283 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1284 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1285 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1286 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1287 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1288 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1289 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1290 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1291 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1292 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1293 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1294 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1295 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1296 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1297 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1298 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1299 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1300 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1301 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1302 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1303 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1304 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1305 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1306 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1307 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1308 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1309 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1310 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1311 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1312 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1313 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1314 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1323 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1324 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
1325 INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1328 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1329 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1330 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1331 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1333 "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1334 "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1335 "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1336 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1337 "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1338 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1341 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1342 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1343 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1344 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1345 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1346 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1349 "mmc0-1bit-a", "mmc0-4bit-a",
1350 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1353 "mmc1-1bit-d", "mmc1-4bit-d",
1354 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1357 "mmc2-1bit-b", "mmc2-4bit-b",
1358 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1361 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1362 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1364 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
1365 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1366 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1367 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1368 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
1369 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1370 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1371 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1372 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
1373 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
1375 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1376 "lcd-special", "lcd-generic",
1386 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1399 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1400 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1401 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1402 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1403 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1404 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1545 INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1546 INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1547 INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1548 INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1549 INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1550 INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1551 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1553 INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1554 INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1555 INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1556 INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1557 INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1558 INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1559 INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1560 INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1561 INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1562 INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1563 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1564 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1565 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1566 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1567 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1568 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1569 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1570 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1571 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1572 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1573 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1574 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1575 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1576 INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1577 INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1578 INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1579 INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1580 INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1581 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1582 INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1583 INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1584 INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1585 INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1586 INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1587 INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1588 INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1589 INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1590 INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1591 INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1592 INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1594 INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1595 INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1596 INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1597 INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1598 INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1599 INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1600 INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1605 INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1606 INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1608 INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1610 INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1612 INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1615 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1616 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1617 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1618 static const char *jz4775_uart3_groups[] = { "uart3-data", };
1620 "ssi-dt-a", "ssi-dt-d",
1621 "ssi-dr-a", "ssi-dr-d",
1622 "ssi-clk-a", "ssi-clk-d",
1623 "ssi-gpc",
1624 "ssi-ce0-a", "ssi-ce0-d",
1625 "ssi-ce1",
1628 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1629 "mmc0-1bit-e", "mmc0-4bit-e",
1632 "mmc1-1bit-d", "mmc1-4bit-d",
1633 "mmc1-1bit-e", "mmc1-4bit-e",
1636 "mmc2-1bit-b", "mmc2-4bit-b",
1637 "mmc2-1bit-e", "mmc2-4bit-e",
1640 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1641 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1643 static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1644 static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1645 static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1646 static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1647 static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1648 static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1650 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1653 static const char *jz4775_cim_groups[] = { "cim-data", };
1655 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1656 "lcd-special", "lcd-generic",
1663 "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1665 static const char *jz4775_otg_groups[] = { "otg-vbus", };
1677 { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), },
1678 { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), },
1679 { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), },
1766 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1767 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1768 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1769 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1770 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1771 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1772 INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1774 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1775 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1776 INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1777 INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1778 INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1779 INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1780 INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1781 INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1782 INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1783 INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1784 INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1785 INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1786 INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1787 INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1788 INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1789 INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1790 INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1791 INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1792 INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1793 INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1794 INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1795 INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1796 INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1797 INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1798 INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1799 INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1800 INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1801 INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1802 INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1803 INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1804 INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1805 INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1806 INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1807 INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1808 INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1809 INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1810 INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1811 INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1812 INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1813 INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1814 INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1815 INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1816 INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1817 INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1818 INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1819 INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1820 INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1821 INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1823 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1824 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1825 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1826 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1827 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1828 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1829 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1830 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1831 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1832 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1833 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1834 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1835 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1836 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1837 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1838 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1839 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1840 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1841 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1842 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1843 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1844 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1845 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1846 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1847 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1848 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1849 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1850 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1851 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1852 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1853 INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1854 INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1855 INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1857 INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1858 INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1860 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1861 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1862 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1863 INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1864 INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1865 INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1866 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1867 INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1868 INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1879 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1880 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1882 "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1883 "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1884 "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1885 "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1886 "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1887 "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1890 "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1891 "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1892 "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1893 "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1894 "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1895 "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1898 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1899 "mmc0-1bit-e", "mmc0-4bit-e",
1902 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1905 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1908 "nemc-data", "nemc-cle-ale", "nemc-addr",
1909 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1911 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1912 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1914 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1917 static const char *jz4780_cim_groups[] = { "cim-data", };
1918 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1932 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1933 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1934 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1935 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1936 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1937 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1955 { "hdmi-ddc", jz4780_hdmi_ddc_groups,
2055 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2056 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2057 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2058 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2059 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2060 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2061 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
2062 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2063 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2064 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2065 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2066 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2067 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2068 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2069 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2070 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2071 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2072 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2073 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2074 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2075 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2076 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2077 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2078 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2079 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2080 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2081 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2082 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2083 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2084 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2085 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2086 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2087 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2088 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2089 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2090 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2091 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2092 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2093 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2094 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2095 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2096 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2097 INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2098 INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2099 INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2100 INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
2101 INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2102 INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
2103 INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2104 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2105 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
2114 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2116 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2118 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2119 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2121 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2122 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2123 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2124 "ssi-gpc-a-20", "ssi-gpc-a-31",
2125 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2126 "ssi-ce1-a-21", "ssi-ce1-a-30",
2129 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2132 "mmc1-1bit", "mmc1-4bit",
2135 "emc-8bit-data", "emc-16bit-data",
2136 "emc-addr", "emc-rd-we", "emc-wait",
2138 static const char *x1000_cs1_groups[] = { "emc-cs1", };
2139 static const char *x1000_cs2_groups[] = { "emc-cs2", };
2140 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2141 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2142 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
2144 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2146 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2147 static const char *x1000_cim_groups[] = { "cim-data", };
2148 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
2165 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
2166 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
2224 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2225 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2226 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2227 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2228 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2229 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2230 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
2231 INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2232 INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2233 INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2234 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2235 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2236 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2237 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2238 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2239 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2240 INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2241 INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2242 INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2243 INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
2244 INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2245 INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
2246 INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
2254 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2256 "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2258 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2259 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
2260 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2261 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2262 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
2264 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2266 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2267 static const char *x1500_cim_groups[] = { "cim-data", };
2387 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2388 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2389 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
2390 INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2391 INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2392 INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
2393 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2394 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2395 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2396 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2397 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2398 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2399 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2400 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2401 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2402 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2403 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2404 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2405 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2406 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2407 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2408 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2409 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2410 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2411 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2412 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2413 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2414 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2415 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2416 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2417 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2418 INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2419 INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2420 INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2421 INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2422 INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
2423 INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2424 INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
2425 INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2426 INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
2427 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2428 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
2429 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2430 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2431 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2432 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2433 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2434 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2435 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2436 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2437 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2438 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2439 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2440 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2441 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2442 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2443 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2444 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2448 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2449 static const char *x1830_uart1_groups[] = { "uart1-data", };
2450 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2452 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2455 "ssi1-dt-c", "ssi1-dt-d",
2456 "ssi1-dr-c", "ssi1-dr-d",
2457 "ssi1-clk-c", "ssi1-clk-d",
2458 "ssi1-gpc-c", "ssi1-gpc-d",
2459 "ssi1-ce0-c", "ssi1-ce0-d",
2460 "ssi1-ce1-c", "ssi1-ce1-d",
2462 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2463 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2464 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2465 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2466 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
2468 "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2470 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2472 "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
2474 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2475 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2476 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2477 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2478 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2479 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2480 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2481 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2697 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2698 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2699 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
2700 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
2701 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
2702 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
2703 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
2704 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
2705 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
2706 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
2707 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
2708 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
2709 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
2710 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
2711 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
2712 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
2713 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
2714 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
2715 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
2716 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
2717 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
2718 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
2719 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
2720 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
2721 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
2722 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
2723 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
2724 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
2725 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
2726 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
2727 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
2728 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
2729 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
2730 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
2731 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
2732 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
2733 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
2734 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
2735 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
2736 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
2737 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
2738 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
2739 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
2740 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
2741 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
2742 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
2743 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
2744 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
2745 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
2746 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
2747 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
2748 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
2749 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
2750 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
2751 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
2752 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
2753 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
2754 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
2755 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
2756 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
2757 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
2758 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
2759 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
2760 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
2761 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
2762 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
2763 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
2764 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
2765 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
2766 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
2767 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
2768 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
2769 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
2770 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
2771 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
2772 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
2773 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
2774 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
2775 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
2776 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
2777 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
2778 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
2779 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
2780 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
2781 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
2782 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
2783 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
2784 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
2785 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
2786 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
2787 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
2788 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
2789 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
2790 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
2791 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
2792 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
2793 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
2795 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
2796 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
2797 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
2798 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
2799 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
2800 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
2801 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
2802 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
2803 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
2804 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
2805 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
2806 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
2807 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
2808 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
2809 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
2810 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
2811 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
2812 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
2813 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
2814 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
2815 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
2816 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
2817 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
2826 INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
2827 INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
2828 INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
2829 INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
2830 INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
2833 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2834 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2835 static const char *x2000_uart2_groups[] = { "uart2-data", };
2837 "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
2840 "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
2842 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
2843 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
2844 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
2845 static const char *x2000_uart8_groups[] = { "uart8-data", };
2846 static const char *x2000_uart9_groups[] = { "uart9-data", };
2848 "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
2849 "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
2852 "ssi0-dt-b", "ssi0-dt-d",
2853 "ssi0-dr-b", "ssi0-dr-d",
2854 "ssi0-clk-b", "ssi0-clk-d",
2855 "ssi0-ce-b", "ssi0-ce-d",
2858 "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
2859 "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
2860 "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
2861 "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
2863 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
2864 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2865 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
2867 "emc-8bit-data", "emc-16bit-data",
2868 "emc-addr", "emc-rd-we", "emc-wait",
2870 static const char *x2000_cs1_groups[] = { "emc-cs1", };
2871 static const char *x2000_cs2_groups[] = { "emc-cs2", };
2872 static const char *x2000_i2c0_groups[] = { "i2c0-data", };
2873 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
2874 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
2875 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
2876 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
2877 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
2879 "i2s1-data-tx", "i2s1-data-rx",
2880 "i2s1-clk-tx", "i2s1-clk-rx",
2881 "i2s1-sysclk-tx", "i2s1-sysclk-rx",
2884 "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
2885 "i2s2-clk-rx", "i2s2-sysclk-rx",
2888 "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
2889 "i2s3-clk-tx", "i2s3-sysclk-tx",
2892 "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
2894 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
2896 "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
2897 "lcd-slcd-8bit", "lcd-slcd-16bit",
2899 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
2900 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
2901 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
2902 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
2903 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
2904 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
2905 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
2906 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
2915 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
2916 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
2917 static const char *x2000_otg_groups[] = { "otg-vbus", };
2937 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
2938 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
2997 INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2998 INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2999 INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3000 INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3001 INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3002 INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3003 INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3004 INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3005 INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3006 INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3007 INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3008 INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3009 INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3010 INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3011 INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3012 INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3013 INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3014 INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3015 INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3016 INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3017 INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3018 INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3019 INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3020 INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3021 INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3022 INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3023 INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3024 INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3025 INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3026 INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3027 INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3028 INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3029 INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3030 INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3031 INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3032 INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3033 INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3034 INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3035 INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3036 INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3037 INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3038 INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3039 INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3040 INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3041 INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3042 INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3043 INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3044 INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3045 INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3046 INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3047 INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3048 INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3049 INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3050 INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3051 INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3052 INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3053 INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3054 INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3055 INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3056 INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3057 INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3058 INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3059 INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3060 INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3061 INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3062 INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3063 INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3064 INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3065 INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3066 INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3067 INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3068 INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3069 INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3070 INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3071 INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3072 INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3073 INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3074 INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3075 INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3076 INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3077 INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3078 INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3079 INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3080 INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3081 INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3082 INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3083 INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3084 INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3085 INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3086 INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3087 INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3088 INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3089 INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3090 INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3091 INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3092 INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3093 INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3095 INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3096 INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3097 INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3098 INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3099 INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3100 INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3101 INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3102 INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3103 INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3104 INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3105 INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3106 INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3107 INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3108 INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3109 INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3110 INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3111 INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3112 INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3113 INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3114 INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3115 INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3116 INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3117 INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3149 { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
3150 { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
3198 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); in ingenic_gpio_read_reg()
3206 if (jzgc->jzpc->info->version == ID_JZ4730) { in ingenic_gpio_set_bit()
3207 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, in ingenic_gpio_set_bit()
3217 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); in ingenic_gpio_set_bit()
3228 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( in ingenic_gpio_shadow_set_bit()
3229 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); in ingenic_gpio_shadow_set_bit()
3234 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( in ingenic_gpio_shadow_set_bit_load()
3235 jzgc->jzpc->info->reg_offset), in ingenic_gpio_shadow_set_bit_load()
3236 jzgc->gc.base / PINS_PER_GPIO_CHIP); in ingenic_gpio_shadow_set_bit_load()
3243 * JZ4730 function and IRQ registers support two-bits-per-pin in jz4730_gpio_set_bits()
3250 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2)); in jz4730_gpio_set_bits()
3264 if (jzgc->jzpc->info->version >= ID_JZ4770) in ingenic_gpio_set_value()
3266 else if (jzgc->jzpc->info->version >= ID_JZ4740) in ingenic_gpio_set_value()
3301 if (jzgc->jzpc->info->version >= ID_JZ4770) { in irq_set_type()
3304 } else if (jzgc->jzpc->info->version >= ID_JZ4740) { in irq_set_type()
3314 if (jzgc->jzpc->info->version >= ID_X2000) { in irq_set_type()
3319 } else if (jzgc->jzpc->info->version >= ID_X1000) { in irq_set_type()
3333 int irq = irqd->hwirq; in ingenic_gpio_irq_mask()
3335 if (jzgc->jzpc->info->version >= ID_JZ4740) in ingenic_gpio_irq_mask()
3345 int irq = irqd->hwirq; in ingenic_gpio_irq_unmask()
3347 if (jzgc->jzpc->info->version >= ID_JZ4740) in ingenic_gpio_irq_unmask()
3357 int irq = irqd->hwirq; in ingenic_gpio_irq_enable()
3359 if (jzgc->jzpc->info->version >= ID_JZ4770) in ingenic_gpio_irq_enable()
3361 else if (jzgc->jzpc->info->version >= ID_JZ4740) in ingenic_gpio_irq_enable()
3373 int irq = irqd->hwirq; in ingenic_gpio_irq_disable()
3377 if (jzgc->jzpc->info->version >= ID_JZ4770) in ingenic_gpio_irq_disable()
3379 else if (jzgc->jzpc->info->version >= ID_JZ4740) in ingenic_gpio_irq_disable()
3389 int irq = irqd->hwirq; in ingenic_gpio_irq_ack()
3393 (jzgc->jzpc->info->version < ID_X2000)) { in ingenic_gpio_irq_ack()
3405 if (jzgc->jzpc->info->version >= ID_JZ4770) in ingenic_gpio_irq_ack()
3407 else if (jzgc->jzpc->info->version >= ID_JZ4740) in ingenic_gpio_irq_ack()
3432 if ((type == IRQ_TYPE_EDGE_BOTH) && (jzgc->jzpc->info->version < ID_X2000)) { in ingenic_gpio_irq_set_type()
3435 * best we can do is to set up a single-edge interrupt and then in ingenic_gpio_irq_set_type()
3438 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); in ingenic_gpio_irq_set_type()
3443 irq_set_type(jzgc, irqd->hwirq, type); in ingenic_gpio_irq_set_type()
3452 return irq_set_irq_wake(jzgc->irq, on); in ingenic_gpio_irq_set_wake()
3459 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); in ingenic_gpio_irq_handler()
3464 if (jzgc->jzpc->info->version >= ID_JZ4770) in ingenic_gpio_irq_handler()
3466 else if (jzgc->jzpc->info->version >= ID_JZ4740) in ingenic_gpio_irq_handler()
3472 generic_handle_domain_irq(gc->irq.domain, i); in ingenic_gpio_irq_handler()
3494 return pinctrl_gpio_direction_input(gc->base + offset); in ingenic_gpio_direction_input()
3501 return pinctrl_gpio_direction_output(gc->base + offset); in ingenic_gpio_direction_output()
3511 if (jzpc->info->version >= ID_JZ4740) in ingenic_config_pin()
3512 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_config_pin()
3515 regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_config_pin()
3518 if (jzpc->info->version >= ID_JZ4740) in ingenic_config_pin()
3519 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_config_pin()
3522 regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_config_pin()
3532 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + in ingenic_shadow_config_pin()
3539 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), in ingenic_shadow_config_pin_load()
3547 * JZ4730 function and IRQ registers support two-bits-per-pin in jz4730_config_pin_function()
3555 regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg, in jz4730_config_pin_function()
3566 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); in ingenic_get_pin_config()
3574 struct ingenic_pinctrl *jzpc = jzgc->jzpc; in ingenic_gpio_get_direction()
3575 unsigned int pin = gc->base + offset; in ingenic_gpio_get_direction()
3577 if (jzpc->info->version >= ID_JZ4770) { in ingenic_gpio_get_direction()
3582 } else if (jzpc->info->version == ID_JZ4730) { in ingenic_gpio_get_direction()
3610 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); in ingenic_gpio_irq_request()
3614 return gpiochip_reqres_irq(gpio_chip, data->hwirq); in ingenic_gpio_irq_request()
3621 return gpiochip_relres_irq(gpio_chip, data->hwirq); in ingenic_gpio_irq_release()
3630 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", in ingenic_pinmux_set_pin_fn()
3633 if (jzpc->info->version >= ID_X1000) { in ingenic_pinmux_set_pin_fn()
3639 } else if (jzpc->info->version >= ID_JZ4770) { in ingenic_pinmux_set_pin_fn()
3644 } else if (jzpc->info->version >= ID_JZ4740) { in ingenic_pinmux_set_pin_fn()
3668 return -EINVAL; in ingenic_pinmux_set_mux()
3672 return -EINVAL; in ingenic_pinmux_set_mux()
3674 dev_dbg(pctldev->dev, "enable function %s group %s\n", in ingenic_pinmux_set_mux()
3675 func->name, grp->name); in ingenic_pinmux_set_mux()
3677 mode = (uintptr_t)grp->data; in ingenic_pinmux_set_mux()
3679 for (i = 0; i < grp->num_pins; i++) in ingenic_pinmux_set_mux()
3680 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode); in ingenic_pinmux_set_mux()
3682 pin_modes = grp->data; in ingenic_pinmux_set_mux()
3684 for (i = 0; i < grp->num_pins; i++) in ingenic_pinmux_set_mux()
3685 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); in ingenic_pinmux_set_mux()
3699 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", in ingenic_pinmux_gpio_set_direction()
3702 if (jzpc->info->version >= ID_X1000) { in ingenic_pinmux_gpio_set_direction()
3707 } else if (jzpc->info->version >= ID_JZ4770) { in ingenic_pinmux_gpio_set_direction()
3711 } else if (jzpc->info->version >= ID_JZ4740) { in ingenic_pinmux_gpio_set_direction()
3743 if (jzpc->info->version >= ID_X2000) { in ingenic_pinconf_get()
3746 (jzpc->info->pull_ups[offt] & BIT(idx)); in ingenic_pinconf_get()
3749 (jzpc->info->pull_downs[offt] & BIT(idx)); in ingenic_pinconf_get()
3751 } else if (jzpc->info->version >= ID_X1830) { in ingenic_pinconf_get()
3756 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_pinconf_get()
3759 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_pinconf_get()
3764 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx)); in ingenic_pinconf_get()
3765 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx)); in ingenic_pinconf_get()
3768 if (jzpc->info->version >= ID_JZ4770) in ingenic_pinconf_get()
3770 else if (jzpc->info->version >= ID_JZ4740) in ingenic_pinconf_get()
3775 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx)); in ingenic_pinconf_get()
3776 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx)); in ingenic_pinconf_get()
3782 return -EINVAL; in ingenic_pinconf_get()
3788 return -EINVAL; in ingenic_pinconf_get()
3794 return -EINVAL; in ingenic_pinconf_get()
3799 if (jzpc->info->version >= ID_X2000) in ingenic_pinconf_get()
3801 else if (jzpc->info->version >= ID_X1830) in ingenic_pinconf_get()
3804 return -EINVAL; in ingenic_pinconf_get()
3810 if (jzpc->info->version >= ID_X2000) in ingenic_pinconf_get()
3812 else if (jzpc->info->version >= ID_X1830) in ingenic_pinconf_get()
3815 return -EINVAL; in ingenic_pinconf_get()
3821 return -ENOTSUPP; in ingenic_pinconf_get()
3831 if (jzpc->info->version >= ID_X2000) { in ingenic_set_bias()
3849 } else if (jzpc->info->version >= ID_X1830) { in ingenic_set_bias()
3856 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_set_bias()
3858 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_set_bias()
3861 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_set_bias()
3863 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + in ingenic_set_bias()
3867 } else if (jzpc->info->version >= ID_JZ4770) { in ingenic_set_bias()
3869 } else if (jzpc->info->version >= ID_JZ4740) { in ingenic_set_bias()
3879 if (jzpc->info->version >= ID_X2000) in ingenic_set_schmitt_trigger()
3888 if (jzpc->info->version >= ID_JZ4770) in ingenic_set_output_level()
3890 else if (jzpc->info->version >= ID_JZ4740) in ingenic_set_output_level()
3899 if (jzpc->info->version >= ID_X2000) in ingenic_set_slew_rate()
3924 return -ENOTSUPP; in ingenic_pinconf_set()
3933 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", in ingenic_pinconf_set()
3939 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) in ingenic_pinconf_set()
3940 return -EINVAL; in ingenic_pinconf_set()
3941 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", in ingenic_pinconf_set()
3947 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) in ingenic_pinconf_set()
3948 return -EINVAL; in ingenic_pinconf_set()
3949 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", in ingenic_pinconf_set()
3955 if (jzpc->info->version < ID_X1830) in ingenic_pinconf_set()
3956 return -EINVAL; in ingenic_pinconf_set()
3970 if (jzpc->info->version < ID_X1830) in ingenic_pinconf_set()
3971 return -EINVAL; in ingenic_pinconf_set()
3998 return -ENOTSUPP; in ingenic_pinconf_group_get()
4002 return -ENOTSUPP; in ingenic_pinconf_group_get()
4047 { .compatible = "ingenic,jz4730-gpio" },
4048 { .compatible = "ingenic,jz4740-gpio" },
4049 { .compatible = "ingenic,jz4725b-gpio" },
4050 { .compatible = "ingenic,jz4750-gpio" },
4051 { .compatible = "ingenic,jz4755-gpio" },
4052 { .compatible = "ingenic,jz4760-gpio" },
4053 { .compatible = "ingenic,jz4770-gpio" },
4054 { .compatible = "ingenic,jz4775-gpio" },
4055 { .compatible = "ingenic,jz4780-gpio" },
4056 { .compatible = "ingenic,x1000-gpio" },
4057 { .compatible = "ingenic,x1830-gpio" },
4058 { .compatible = "ingenic,x2000-gpio" },
4059 { .compatible = "ingenic,x2100-gpio" },
4067 struct device *dev = jzpc->dev; in ingenic_gpio_probe()
4080 return -ENOMEM; in ingenic_gpio_probe()
4082 jzgc->jzpc = jzpc; in ingenic_gpio_probe()
4083 jzgc->reg_base = bank * jzpc->info->reg_offset; in ingenic_gpio_probe()
4085 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); in ingenic_gpio_probe()
4086 if (!jzgc->gc.label) in ingenic_gpio_probe()
4087 return -ENOMEM; in ingenic_gpio_probe()
4093 jzgc->gc.base = bank * 32; in ingenic_gpio_probe()
4095 jzgc->gc.ngpio = 32; in ingenic_gpio_probe()
4096 jzgc->gc.parent = dev; in ingenic_gpio_probe()
4097 jzgc->gc.of_node = node; in ingenic_gpio_probe()
4098 jzgc->gc.owner = THIS_MODULE; in ingenic_gpio_probe()
4100 jzgc->gc.set = ingenic_gpio_set; in ingenic_gpio_probe()
4101 jzgc->gc.get = ingenic_gpio_get; in ingenic_gpio_probe()
4102 jzgc->gc.direction_input = ingenic_gpio_direction_input; in ingenic_gpio_probe()
4103 jzgc->gc.direction_output = ingenic_gpio_direction_output; in ingenic_gpio_probe()
4104 jzgc->gc.get_direction = ingenic_gpio_get_direction; in ingenic_gpio_probe()
4105 jzgc->gc.request = gpiochip_generic_request; in ingenic_gpio_probe()
4106 jzgc->gc.free = gpiochip_generic_free; in ingenic_gpio_probe()
4108 jzgc->irq = irq_of_parse_and_map(node, 0); in ingenic_gpio_probe()
4109 if (!jzgc->irq) in ingenic_gpio_probe()
4110 return -EINVAL; in ingenic_gpio_probe()
4112 jzgc->irq_chip.name = jzgc->gc.label; in ingenic_gpio_probe()
4113 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; in ingenic_gpio_probe()
4114 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; in ingenic_gpio_probe()
4115 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; in ingenic_gpio_probe()
4116 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; in ingenic_gpio_probe()
4117 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; in ingenic_gpio_probe()
4118 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; in ingenic_gpio_probe()
4119 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; in ingenic_gpio_probe()
4120 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; in ingenic_gpio_probe()
4121 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; in ingenic_gpio_probe()
4122 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; in ingenic_gpio_probe()
4124 girq = &jzgc->gc.irq; in ingenic_gpio_probe()
4125 girq->chip = &jzgc->irq_chip; in ingenic_gpio_probe()
4126 girq->parent_handler = ingenic_gpio_irq_handler; in ingenic_gpio_probe()
4127 girq->num_parents = 1; in ingenic_gpio_probe()
4128 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), in ingenic_gpio_probe()
4130 if (!girq->parents) in ingenic_gpio_probe()
4131 return -ENOMEM; in ingenic_gpio_probe()
4133 girq->parents[0] = jzgc->irq; in ingenic_gpio_probe()
4134 girq->default_type = IRQ_TYPE_NONE; in ingenic_gpio_probe()
4135 girq->handler = handle_level_irq; in ingenic_gpio_probe()
4137 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); in ingenic_gpio_probe()
4146 struct device *dev = &pdev->dev; in ingenic_pinctrl_probe()
4159 return -EINVAL; in ingenic_pinctrl_probe()
4164 return -ENOMEM; in ingenic_pinctrl_probe()
4171 regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset; in ingenic_pinctrl_probe()
4173 jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); in ingenic_pinctrl_probe()
4174 if (IS_ERR(jzpc->map)) { in ingenic_pinctrl_probe()
4176 return PTR_ERR(jzpc->map); in ingenic_pinctrl_probe()
4179 jzpc->dev = dev; in ingenic_pinctrl_probe()
4180 jzpc->info = chip_info; in ingenic_pinctrl_probe()
4182 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); in ingenic_pinctrl_probe()
4184 return -ENOMEM; in ingenic_pinctrl_probe()
4187 pctl_desc->name = dev_name(dev); in ingenic_pinctrl_probe()
4188 pctl_desc->owner = THIS_MODULE; in ingenic_pinctrl_probe()
4189 pctl_desc->pctlops = &ingenic_pctlops; in ingenic_pinctrl_probe()
4190 pctl_desc->pmxops = &ingenic_pmxops; in ingenic_pinctrl_probe()
4191 pctl_desc->confops = &ingenic_confops; in ingenic_pinctrl_probe()
4192 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; in ingenic_pinctrl_probe()
4193 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, in ingenic_pinctrl_probe()
4194 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); in ingenic_pinctrl_probe()
4195 if (!jzpc->pdesc) in ingenic_pinctrl_probe()
4196 return -ENOMEM; in ingenic_pinctrl_probe()
4198 for (i = 0; i < pctl_desc->npins; i++) { in ingenic_pinctrl_probe()
4199 jzpc->pdesc[i].number = i; in ingenic_pinctrl_probe()
4200 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", in ingenic_pinctrl_probe()
4205 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); in ingenic_pinctrl_probe()
4206 if (IS_ERR(jzpc->pctl)) { in ingenic_pinctrl_probe()
4208 return PTR_ERR(jzpc->pctl); in ingenic_pinctrl_probe()
4211 for (i = 0; i < chip_info->num_groups; i++) { in ingenic_pinctrl_probe()
4212 const struct group_desc *group = &chip_info->groups[i]; in ingenic_pinctrl_probe()
4214 err = pinctrl_generic_add_group(jzpc->pctl, group->name, in ingenic_pinctrl_probe()
4215 group->pins, group->num_pins, group->data); in ingenic_pinctrl_probe()
4218 group->name); in ingenic_pinctrl_probe()
4223 for (i = 0; i < chip_info->num_functions; i++) { in ingenic_pinctrl_probe()
4224 const struct function_desc *func = &chip_info->functions[i]; in ingenic_pinctrl_probe()
4226 err = pinmux_generic_add_function(jzpc->pctl, func->name, in ingenic_pinctrl_probe()
4227 func->group_names, func->num_group_names, in ingenic_pinctrl_probe()
4228 func->data); in ingenic_pinctrl_probe()
4231 func->name); in ingenic_pinctrl_probe()
4236 dev_set_drvdata(dev, jzpc->map); in ingenic_pinctrl_probe()
4238 for_each_child_of_node(dev->of_node, node) { in ingenic_pinctrl_probe()
4255 .compatible = "ingenic,jz4730-pinctrl",
4259 .compatible = "ingenic,jz4740-pinctrl",
4263 .compatible = "ingenic,jz4725b-pinctrl",
4267 .compatible = "ingenic,jz4750-pinctrl",
4271 .compatible = "ingenic,jz4755-pinctrl",
4275 .compatible = "ingenic,jz4760-pinctrl",
4279 .compatible = "ingenic,jz4760b-pinctrl",
4283 .compatible = "ingenic,jz4770-pinctrl",
4287 .compatible = "ingenic,jz4775-pinctrl",
4291 .compatible = "ingenic,jz4780-pinctrl",
4295 .compatible = "ingenic,x1000-pinctrl",
4299 .compatible = "ingenic,x1000e-pinctrl",
4303 .compatible = "ingenic,x1500-pinctrl",
4307 .compatible = "ingenic,x1830-pinctrl",
4311 .compatible = "ingenic,x2000-pinctrl",
4315 .compatible = "ingenic,x2000e-pinctrl",
4319 .compatible = "ingenic,x2100-pinctrl",
4327 .name = "pinctrl-ingenic",