Lines Matching +full:pio +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
28 #include "pinctrl-at91.h"
40 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
41 int pioc_virq; /* PIO bank Linux virtual interrupt */
42 int pioc_idx; /* PIO bank index */
43 void __iomem *regbase; /* PIO bank virtual address */
74 * from the corresponding device datasheet. This value is different for pins
97 * struct at91_pmx_func - describes AT91 pinmux functions
117 * struct at91_pmx_pin - describes an At91 pin mux
131 * struct at91_pin_group - describes an At91 pin group
134 * array is the same as pins.
135 * @pins: an array of discrete physical pins used in this group, taken
136 * from the driver-local pin enumeration space
137 * @npins: the number of pins in this group array, i.e. the number of
138 * elements in .pins so we can iterate over that array
143 unsigned int *pins; member
148 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
173 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
174 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
175 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
176 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
177 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
178 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
179 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
180 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
181 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
182 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
183 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
184 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
185 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
186 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
187 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
189 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
190 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
223 for (i = 0; i < info->ngroups; i++) { in at91_pinctrl_find_group_by_name()
224 if (strcmp(info->groups[i].name, name)) in at91_pinctrl_find_group_by_name()
227 grp = &info->groups[i]; in at91_pinctrl_find_group_by_name()
228 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); in at91_pinctrl_find_group_by_name()
239 return info->ngroups; in at91_get_groups_count()
247 return info->groups[selector].name; in at91_get_group_name()
251 const unsigned **pins, in at91_get_group_pins() argument
256 if (selector >= info->ngroups) in at91_get_group_pins()
257 return -EINVAL; in at91_get_group_pins()
259 *pins = info->groups[selector].pins; in at91_get_group_pins()
260 *npins = info->groups[selector].npins; in at91_get_group_pins()
268 seq_printf(s, "%s", dev_name(pctldev->dev)); in at91_pin_dbg_show()
284 * config maps for pins in at91_dt_node_to_map()
286 grp = at91_pinctrl_find_group_by_name(info, np->name); in at91_dt_node_to_map()
288 dev_err(info->dev, "unable to find group for node %pOFn\n", in at91_dt_node_to_map()
290 return -EINVAL; in at91_dt_node_to_map()
293 map_num += grp->npins; in at91_dt_node_to_map()
294 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), in at91_dt_node_to_map()
297 return -ENOMEM; in at91_dt_node_to_map()
305 devm_kfree(pctldev->dev, new_map); in at91_dt_node_to_map()
306 return -EINVAL; in at91_dt_node_to_map()
309 new_map[0].data.mux.function = parent->name; in at91_dt_node_to_map()
310 new_map[0].data.mux.group = np->name; in at91_dt_node_to_map()
315 for (i = 0; i < grp->npins; i++) { in at91_dt_node_to_map()
318 pin_get_name(pctldev, grp->pins[i]); in at91_dt_node_to_map()
319 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; in at91_dt_node_to_map()
323 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in at91_dt_node_to_map()
324 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in at91_dt_node_to_map()
349 return gpio_chips[bank]->regbase; in pin_to_controller()
367 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); in two_bit_pin_value_shift_amount()
386 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) in at91_mux_disable_interrupt() argument
388 writel_relaxed(mask, pio + PIO_IDR); in at91_mux_disable_interrupt()
391 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) in at91_mux_get_pullup() argument
393 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); in at91_mux_get_pullup()
396 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) in at91_mux_set_pullup() argument
399 writel_relaxed(mask, pio + PIO_PPDDR); in at91_mux_set_pullup()
401 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); in at91_mux_set_pullup()
404 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val) in at91_mux_get_output() argument
406 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1; in at91_mux_get_output()
407 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1; in at91_mux_get_output()
410 static void at91_mux_set_output(void __iomem *pio, unsigned int mask, in at91_mux_set_output() argument
413 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_mux_set_output()
414 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); in at91_mux_set_output()
417 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) in at91_mux_get_multidrive() argument
419 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; in at91_mux_get_multidrive()
422 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) in at91_mux_set_multidrive() argument
424 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); in at91_mux_set_multidrive()
427 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) in at91_mux_set_A_periph() argument
429 writel_relaxed(mask, pio + PIO_ASR); in at91_mux_set_A_periph()
432 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) in at91_mux_set_B_periph() argument
434 writel_relaxed(mask, pio + PIO_BSR); in at91_mux_set_B_periph()
437 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_A_periph() argument
440 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, in at91_mux_pio3_set_A_periph()
441 pio + PIO_ABCDSR1); in at91_mux_pio3_set_A_periph()
442 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_A_periph()
443 pio + PIO_ABCDSR2); in at91_mux_pio3_set_A_periph()
446 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_B_periph() argument
448 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, in at91_mux_pio3_set_B_periph()
449 pio + PIO_ABCDSR1); in at91_mux_pio3_set_B_periph()
450 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_B_periph()
451 pio + PIO_ABCDSR2); in at91_mux_pio3_set_B_periph()
454 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_C_periph() argument
456 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); in at91_mux_pio3_set_C_periph()
457 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); in at91_mux_pio3_set_C_periph()
460 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_D_periph() argument
462 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); in at91_mux_pio3_set_D_periph()
463 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); in at91_mux_pio3_set_D_periph()
466 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_get_periph() argument
470 if (readl_relaxed(pio + PIO_PSR) & mask) in at91_mux_pio3_get_periph()
473 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); in at91_mux_pio3_get_periph()
474 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); in at91_mux_pio3_get_periph()
479 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) in at91_mux_get_periph() argument
483 if (readl_relaxed(pio + PIO_PSR) & mask) in at91_mux_get_periph()
486 select = readl_relaxed(pio + PIO_ABSR) & mask; in at91_mux_get_periph()
491 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) in at91_mux_get_deglitch() argument
493 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; in at91_mux_get_deglitch()
496 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_set_deglitch() argument
498 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); in at91_mux_set_deglitch()
501 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_deglitch() argument
503 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) in at91_mux_pio3_get_deglitch()
504 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); in at91_mux_pio3_get_deglitch()
509 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_pio3_set_deglitch() argument
512 writel_relaxed(mask, pio + PIO_IFSCDR); in at91_mux_pio3_set_deglitch()
513 at91_mux_set_deglitch(pio, mask, is_on); in at91_mux_pio3_set_deglitch()
516 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) in at91_mux_pio3_get_debounce() argument
518 *div = readl_relaxed(pio + PIO_SCDR); in at91_mux_pio3_get_debounce()
520 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && in at91_mux_pio3_get_debounce()
521 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); in at91_mux_pio3_get_debounce()
524 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, in at91_mux_pio3_set_debounce() argument
528 writel_relaxed(mask, pio + PIO_IFSCER); in at91_mux_pio3_set_debounce()
529 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); in at91_mux_pio3_set_debounce()
530 writel_relaxed(mask, pio + PIO_IFER); in at91_mux_pio3_set_debounce()
532 writel_relaxed(mask, pio + PIO_IFSCDR); in at91_mux_pio3_set_debounce()
535 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_pulldown() argument
537 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); in at91_mux_pio3_get_pulldown()
540 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_pio3_set_pulldown() argument
543 writel_relaxed(mask, pio + PIO_PUDR); in at91_mux_pio3_set_pulldown()
545 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); in at91_mux_pio3_set_pulldown()
548 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) in at91_mux_pio3_disable_schmitt_trig() argument
550 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); in at91_mux_pio3_disable_schmitt_trig()
553 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_schmitt_trig() argument
555 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; in at91_mux_pio3_get_schmitt_trig()
567 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, in at91_mux_sama5d3_get_drivestrength() argument
570 unsigned tmp = read_drive_strength(pio + in at91_mux_sama5d3_get_drivestrength()
581 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, in at91_mux_sam9x5_get_drivestrength() argument
584 unsigned tmp = read_drive_strength(pio + in at91_mux_sam9x5_get_drivestrength()
589 tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp; in at91_mux_sam9x5_get_drivestrength()
594 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio, in at91_mux_sam9x60_get_drivestrength() argument
597 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); in at91_mux_sam9x60_get_drivestrength()
605 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin) in at91_mux_sam9x60_get_slewrate() argument
607 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); in at91_mux_sam9x60_get_slewrate()
626 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sama5d3_set_drivestrength() argument
634 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); in at91_mux_sama5d3_set_drivestrength()
637 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sam9x5_set_drivestrength() argument
646 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting; in at91_mux_sam9x5_set_drivestrength()
648 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, in at91_mux_sam9x5_set_drivestrength()
652 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sam9x60_set_drivestrength() argument
662 tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); in at91_mux_sam9x60_set_drivestrength()
670 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1); in at91_mux_sam9x60_set_drivestrength()
673 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, in at91_mux_sam9x60_set_slewrate() argument
681 tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); in at91_mux_sam9x60_set_slewrate()
688 writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR); in at91_mux_sam9x60_set_slewrate()
761 if (pin->mux) { in at91_pin_dbg()
762 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", in at91_pin_dbg()
763 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); in at91_pin_dbg()
765 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", in at91_pin_dbg()
766 pin->bank + 'A', pin->pin, pin->conf); in at91_pin_dbg()
776 if (pin->bank >= gpio_banks) { in pin_check_config()
777 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", in pin_check_config()
778 name, index, pin->bank, gpio_banks); in pin_check_config()
779 return -EINVAL; in pin_check_config()
782 if (!gpio_chips[pin->bank]) { in pin_check_config()
783 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", in pin_check_config()
784 name, index, pin->bank); in pin_check_config()
785 return -ENXIO; in pin_check_config()
788 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { in pin_check_config()
789 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", in pin_check_config()
790 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); in pin_check_config()
791 return -EINVAL; in pin_check_config()
794 if (!pin->mux) in pin_check_config()
797 mux = pin->mux - 1; in pin_check_config()
799 if (mux >= info->nmux) { in pin_check_config()
800 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", in pin_check_config()
801 name, index, mux, info->nmux); in pin_check_config()
802 return -EINVAL; in pin_check_config()
805 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { in pin_check_config()
806 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", in pin_check_config()
807 name, index, mux, pin->bank + 'A', pin->pin); in pin_check_config()
808 return -EINVAL; in pin_check_config()
814 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) in at91_mux_gpio_disable() argument
816 writel_relaxed(mask, pio + PIO_PDR); in at91_mux_gpio_disable()
819 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) in at91_mux_gpio_enable() argument
821 writel_relaxed(mask, pio + PIO_PER); in at91_mux_gpio_enable()
822 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); in at91_mux_gpio_enable()
829 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; in at91_pmx_set()
831 uint32_t npins = info->groups[group].npins; in at91_pmx_set()
834 void __iomem *pio; in at91_pmx_set() local
836 dev_dbg(info->dev, "enable function %s group %s\n", in at91_pmx_set()
837 info->functions[selector].name, info->groups[group].name); in at91_pmx_set()
839 /* first check that all the pins of the group are valid with a valid in at91_pmx_set()
843 ret = pin_check_config(info, info->groups[group].name, i, pin); in at91_pmx_set()
850 at91_pin_dbg(info->dev, pin); in at91_pmx_set()
851 pio = pin_to_controller(info, pin->bank); in at91_pmx_set()
853 if (!pio) in at91_pmx_set()
856 mask = pin_to_mask(pin->pin); in at91_pmx_set()
857 at91_mux_disable_interrupt(pio, mask); in at91_pmx_set()
858 switch (pin->mux) { in at91_pmx_set()
860 at91_mux_gpio_enable(pio, mask, 1); in at91_pmx_set()
863 info->ops->mux_A_periph(pio, mask); in at91_pmx_set()
866 info->ops->mux_B_periph(pio, mask); in at91_pmx_set()
869 if (!info->ops->mux_C_periph) in at91_pmx_set()
870 return -EINVAL; in at91_pmx_set()
871 info->ops->mux_C_periph(pio, mask); in at91_pmx_set()
874 if (!info->ops->mux_D_periph) in at91_pmx_set()
875 return -EINVAL; in at91_pmx_set()
876 info->ops->mux_D_periph(pio, mask); in at91_pmx_set()
879 if (pin->mux) in at91_pmx_set()
880 at91_mux_gpio_disable(pio, mask); in at91_pmx_set()
890 return info->nfunctions; in at91_pmx_get_funcs_count()
898 return info->functions[selector].name; in at91_pmx_get_func_name()
907 *groups = info->functions[selector].groups; in at91_pmx_get_groups()
908 *num_groups = info->functions[selector].ngroups; in at91_pmx_get_groups()
923 dev_err(npct->dev, "invalid range\n"); in at91_gpio_request_enable()
924 return -EINVAL; in at91_gpio_request_enable()
926 if (!range->gc) { in at91_gpio_request_enable()
927 dev_err(npct->dev, "missing GPIO chip in range\n"); in at91_gpio_request_enable()
928 return -EINVAL; in at91_gpio_request_enable()
930 chip = range->gc; in at91_gpio_request_enable()
933 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); in at91_gpio_request_enable()
935 mask = 1 << (offset - chip->base); in at91_gpio_request_enable()
937 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", in at91_gpio_request_enable()
938 offset, 'A' + range->id, offset - chip->base, mask); in at91_gpio_request_enable()
940 writel_relaxed(mask, at91_chip->regbase + PIO_PER); in at91_gpio_request_enable()
951 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); in at91_gpio_disable_free()
968 void __iomem *pio; in at91_pinconf_get() local
974 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); in at91_pinconf_get()
975 pio = pin_to_controller(info, pin_to_bank(pin_id)); in at91_pinconf_get()
977 if (!pio) in at91_pinconf_get()
978 return -EINVAL; in at91_pinconf_get()
982 if (at91_mux_get_multidrive(pio, pin)) in at91_pinconf_get()
985 if (at91_mux_get_pullup(pio, pin)) in at91_pinconf_get()
988 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) in at91_pinconf_get()
990 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) in at91_pinconf_get()
992 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) in at91_pinconf_get()
994 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) in at91_pinconf_get()
996 if (info->ops->get_drivestrength) in at91_pinconf_get()
997 *config |= (info->ops->get_drivestrength(pio, pin) in at91_pinconf_get()
999 if (info->ops->get_slewrate) in at91_pinconf_get()
1000 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT); in at91_pinconf_get()
1001 if (at91_mux_get_output(pio, pin, &out)) in at91_pinconf_get()
1013 void __iomem *pio; in at91_pinconf_set() local
1021 dev_dbg(info->dev, in at91_pinconf_set()
1024 pio = pin_to_controller(info, pin_to_bank(pin_id)); in at91_pinconf_set()
1026 if (!pio) in at91_pinconf_set()
1027 return -EINVAL; in at91_pinconf_set()
1033 return -EINVAL; in at91_pinconf_set()
1035 at91_mux_set_output(pio, mask, config & OUTPUT, in at91_pinconf_set()
1037 at91_mux_set_pullup(pio, mask, config & PULL_UP); in at91_pinconf_set()
1038 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); in at91_pinconf_set()
1039 if (info->ops->set_deglitch) in at91_pinconf_set()
1040 info->ops->set_deglitch(pio, mask, config & DEGLITCH); in at91_pinconf_set()
1041 if (info->ops->set_debounce) in at91_pinconf_set()
1042 info->ops->set_debounce(pio, mask, config & DEBOUNCE, in at91_pinconf_set()
1044 if (info->ops->set_pulldown) in at91_pinconf_set()
1045 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); in at91_pinconf_set()
1046 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) in at91_pinconf_set()
1047 info->ops->disable_schmitt_trig(pio, mask); in at91_pinconf_set()
1048 if (info->ops->set_drivestrength) in at91_pinconf_set()
1049 info->ops->set_drivestrength(pio, pin, in at91_pinconf_set()
1052 if (info->ops->set_slewrate) in at91_pinconf_set()
1053 info->ops->set_slewrate(pio, pin, in at91_pinconf_set()
1127 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1137 info->nactive_banks++; in at91_pinctrl_child_count()
1139 info->nfunctions++; in at91_pinctrl_child_count()
1140 info->ngroups += of_get_child_count(child); in at91_pinctrl_child_count()
1152 list = of_get_property(np, "atmel,mux-mask", &size); in at91_pinctrl_mux_mask()
1154 dev_err(info->dev, "can not read the mux-mask of %d\n", size); in at91_pinctrl_mux_mask()
1155 return -EINVAL; in at91_pinctrl_mux_mask()
1160 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); in at91_pinctrl_mux_mask()
1161 return -EINVAL; in at91_pinctrl_mux_mask()
1163 info->nmux = size / gpio_banks; in at91_pinctrl_mux_mask()
1165 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32), in at91_pinctrl_mux_mask()
1167 if (!info->mux_mask) in at91_pinctrl_mux_mask()
1168 return -ENOMEM; in at91_pinctrl_mux_mask()
1170 ret = of_property_read_u32_array(np, "atmel,mux-mask", in at91_pinctrl_mux_mask()
1171 info->mux_mask, size); in at91_pinctrl_mux_mask()
1173 dev_err(info->dev, "can not read the mux-mask of %d\n", size); in at91_pinctrl_mux_mask()
1186 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); in at91_pinctrl_parse_groups()
1189 grp->name = np->name; in at91_pinctrl_parse_groups()
1192 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, in at91_pinctrl_parse_groups()
1193 * do sanity check and calculate pins number in at91_pinctrl_parse_groups()
1195 list = of_get_property(np, "atmel,pins", &size); in at91_pinctrl_parse_groups()
1199 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); in at91_pinctrl_parse_groups()
1200 return -EINVAL; in at91_pinctrl_parse_groups()
1203 grp->npins = size / 4; in at91_pinctrl_parse_groups()
1204 pin = grp->pins_conf = devm_kcalloc(info->dev, in at91_pinctrl_parse_groups()
1205 grp->npins, in at91_pinctrl_parse_groups()
1208 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), in at91_pinctrl_parse_groups()
1210 if (!grp->pins_conf || !grp->pins) in at91_pinctrl_parse_groups()
1211 return -ENOMEM; in at91_pinctrl_parse_groups()
1214 pin->bank = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1215 pin->pin = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1216 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; in at91_pinctrl_parse_groups()
1217 pin->mux = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1218 pin->conf = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1220 at91_pin_dbg(info->dev, pin); in at91_pinctrl_parse_groups()
1237 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); in at91_pinctrl_parse_functions()
1239 func = &info->functions[index]; in at91_pinctrl_parse_functions()
1242 func->name = np->name; in at91_pinctrl_parse_functions()
1243 func->ngroups = of_get_child_count(np); in at91_pinctrl_parse_functions()
1244 if (func->ngroups == 0) { in at91_pinctrl_parse_functions()
1245 dev_err(info->dev, "no groups defined\n"); in at91_pinctrl_parse_functions()
1246 return -EINVAL; in at91_pinctrl_parse_functions()
1248 func->groups = devm_kcalloc(info->dev, in at91_pinctrl_parse_functions()
1249 func->ngroups, sizeof(char *), GFP_KERNEL); in at91_pinctrl_parse_functions()
1250 if (!func->groups) in at91_pinctrl_parse_functions()
1251 return -ENOMEM; in at91_pinctrl_parse_functions()
1254 func->groups[i] = child->name; in at91_pinctrl_parse_functions()
1255 grp = &info->groups[grp_index++]; in at91_pinctrl_parse_functions()
1267 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1268 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1269 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1270 { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1280 struct device_node *np = pdev->dev.of_node; in at91_pinctrl_probe_dt()
1284 return -ENODEV; in at91_pinctrl_probe_dt()
1286 info->dev = &pdev->dev; in at91_pinctrl_probe_dt()
1287 info->ops = (const struct at91_pinctrl_mux_ops *) in at91_pinctrl_probe_dt()
1288 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; in at91_pinctrl_probe_dt()
1292 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); in at91_pinctrl_probe_dt()
1293 return -EINVAL; in at91_pinctrl_probe_dt()
1300 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); in at91_pinctrl_probe_dt()
1302 dev_dbg(&pdev->dev, "mux-mask\n"); in at91_pinctrl_probe_dt()
1303 tmp = info->mux_mask; in at91_pinctrl_probe_dt()
1305 for (j = 0; j < info->nmux; j++, tmp++) { in at91_pinctrl_probe_dt()
1306 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); in at91_pinctrl_probe_dt()
1310 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in at91_pinctrl_probe_dt()
1311 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); in at91_pinctrl_probe_dt()
1312 info->functions = devm_kcalloc(&pdev->dev, in at91_pinctrl_probe_dt()
1313 info->nfunctions, in at91_pinctrl_probe_dt()
1316 if (!info->functions) in at91_pinctrl_probe_dt()
1317 return -ENOMEM; in at91_pinctrl_probe_dt()
1319 info->groups = devm_kcalloc(&pdev->dev, in at91_pinctrl_probe_dt()
1320 info->ngroups, in at91_pinctrl_probe_dt()
1323 if (!info->groups) in at91_pinctrl_probe_dt()
1324 return -ENOMEM; in at91_pinctrl_probe_dt()
1326 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks); in at91_pinctrl_probe_dt()
1327 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in at91_pinctrl_probe_dt()
1328 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); in at91_pinctrl_probe_dt()
1337 dev_err(&pdev->dev, "failed to parse function\n"); in at91_pinctrl_probe_dt()
1352 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); in at91_pinctrl_probe()
1354 return -ENOMEM; in at91_pinctrl_probe()
1369 if (ngpio_chips_enabled < info->nactive_banks) { in at91_pinctrl_probe()
1370 dev_warn(&pdev->dev, in at91_pinctrl_probe()
1372 ngpio_chips_enabled, info->nactive_banks); in at91_pinctrl_probe()
1373 devm_kfree(&pdev->dev, info); in at91_pinctrl_probe()
1374 return -EPROBE_DEFER; in at91_pinctrl_probe()
1377 at91_pinctrl_desc.name = dev_name(&pdev->dev); in at91_pinctrl_probe()
1379 at91_pinctrl_desc.pins = pdesc = in at91_pinctrl_probe()
1380 devm_kcalloc(&pdev->dev, in at91_pinctrl_probe()
1384 if (!at91_pinctrl_desc.pins) in at91_pinctrl_probe()
1385 return -ENOMEM; in at91_pinctrl_probe()
1389 pdesc->number = k; in at91_pinctrl_probe()
1390 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); in at91_pinctrl_probe()
1396 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc, in at91_pinctrl_probe()
1399 if (IS_ERR(info->pctl)) { in at91_pinctrl_probe()
1400 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); in at91_pinctrl_probe()
1401 return PTR_ERR(info->pctl); in at91_pinctrl_probe()
1404 /* We will handle a range of GPIO pins */ in at91_pinctrl_probe()
1407 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); in at91_pinctrl_probe()
1409 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); in at91_pinctrl_probe()
1417 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get_direction() local
1421 osr = readl_relaxed(pio + PIO_OSR); in at91_gpio_get_direction()
1431 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_input() local
1434 writel_relaxed(mask, pio + PIO_ODR); in at91_gpio_direction_input()
1441 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get() local
1445 pdsr = readl_relaxed(pio + PIO_PDSR); in at91_gpio_get()
1453 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set() local
1456 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_gpio_set()
1463 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set_multiple() local
1465 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) in at91_gpio_set_multiple()
1466 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ in at91_gpio_set_multiple()
1467 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); in at91_gpio_set_multiple()
1468 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); in at91_gpio_set_multiple()
1470 writel_relaxed(set_mask, pio + PIO_SODR); in at91_gpio_set_multiple()
1471 writel_relaxed(clear_mask, pio + PIO_CODR); in at91_gpio_set_multiple()
1478 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_output() local
1481 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_gpio_direction_output()
1482 writel_relaxed(mask, pio + PIO_OER); in at91_gpio_direction_output()
1493 void __iomem *pio = at91_gpio->regbase; in at91_gpio_dbg_show() local
1499 mode = at91_gpio->ops->get_periph(pio, mask); in at91_gpio_dbg_show()
1501 gpio_label, chip->label, i); in at91_gpio_dbg_show()
1505 readl_relaxed(pio + PIO_OSR) & mask ? in at91_gpio_dbg_show()
1508 readl_relaxed(pio + PIO_PDSR) & mask ? in at91_gpio_dbg_show()
1512 mode + 'A' - 1); in at91_gpio_dbg_show()
1529 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1537 void __iomem *pio = at91_gpio->regbase; in gpio_irq_mask() local
1538 unsigned mask = 1 << d->hwirq; in gpio_irq_mask()
1540 if (pio) in gpio_irq_mask()
1541 writel_relaxed(mask, pio + PIO_IDR); in gpio_irq_mask()
1547 void __iomem *pio = at91_gpio->regbase; in gpio_irq_unmask() local
1548 unsigned mask = 1 << d->hwirq; in gpio_irq_unmask()
1550 if (pio) in gpio_irq_unmask()
1551 writel_relaxed(mask, pio + PIO_IER); in gpio_irq_unmask()
1561 return -EINVAL; in gpio_irq_type()
1569 void __iomem *pio = at91_gpio->regbase; in alt_gpio_irq_type() local
1570 unsigned mask = 1 << d->hwirq; in alt_gpio_irq_type()
1575 writel_relaxed(mask, pio + PIO_ESR); in alt_gpio_irq_type()
1576 writel_relaxed(mask, pio + PIO_REHLSR); in alt_gpio_irq_type()
1580 writel_relaxed(mask, pio + PIO_ESR); in alt_gpio_irq_type()
1581 writel_relaxed(mask, pio + PIO_FELLSR); in alt_gpio_irq_type()
1585 writel_relaxed(mask, pio + PIO_LSR); in alt_gpio_irq_type()
1586 writel_relaxed(mask, pio + PIO_FELLSR); in alt_gpio_irq_type()
1590 writel_relaxed(mask, pio + PIO_LSR); in alt_gpio_irq_type()
1591 writel_relaxed(mask, pio + PIO_REHLSR); in alt_gpio_irq_type()
1599 writel_relaxed(mask, pio + PIO_AIMDR); in alt_gpio_irq_type()
1603 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq); in alt_gpio_irq_type()
1604 return -EINVAL; in alt_gpio_irq_type()
1608 writel_relaxed(mask, pio + PIO_AIMER); in alt_gpio_irq_type()
1626 unsigned bank = at91_gpio->pioc_idx; in gpio_irq_set_wake()
1627 unsigned mask = 1 << d->hwirq; in gpio_irq_set_wake()
1630 return -EINVAL; in gpio_irq_set_wake()
1637 irq_set_irq_wake(at91_gpio->pioc_virq, state); in gpio_irq_set_wake()
1647 void __iomem *pio; in at91_pinctrl_gpio_suspend() local
1652 pio = gpio_chips[i]->regbase; in at91_pinctrl_gpio_suspend()
1654 backups[i] = readl_relaxed(pio + PIO_IMR); in at91_pinctrl_gpio_suspend()
1655 writel_relaxed(backups[i], pio + PIO_IDR); in at91_pinctrl_gpio_suspend()
1656 writel_relaxed(wakeups[i], pio + PIO_IER); in at91_pinctrl_gpio_suspend()
1659 clk_disable_unprepare(gpio_chips[i]->clock); in at91_pinctrl_gpio_suspend()
1661 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", in at91_pinctrl_gpio_suspend()
1671 void __iomem *pio; in at91_pinctrl_gpio_resume() local
1676 pio = gpio_chips[i]->regbase; in at91_pinctrl_gpio_resume()
1679 clk_prepare_enable(gpio_chips[i]->clock); in at91_pinctrl_gpio_resume()
1681 writel_relaxed(wakeups[i], pio + PIO_IDR); in at91_pinctrl_gpio_resume()
1682 writel_relaxed(backups[i], pio + PIO_IER); in at91_pinctrl_gpio_resume()
1695 void __iomem *pio = at91_gpio->regbase; in gpio_irq_handler() local
1705 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); in gpio_irq_handler()
1707 if (!at91_gpio->next) in gpio_irq_handler()
1709 at91_gpio = at91_gpio->next; in gpio_irq_handler()
1710 pio = at91_gpio->regbase; in gpio_irq_handler()
1711 gpio_chip = &at91_gpio->chip; in gpio_irq_handler()
1716 generic_handle_domain_irq(gpio_chip->irq.domain, n); in gpio_irq_handler()
1719 /* now it may re-trigger */ in gpio_irq_handler()
1727 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); in at91_gpio_of_irq_setup()
1732 gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), in at91_gpio_of_irq_setup()
1735 return -ENOMEM; in at91_gpio_of_irq_setup()
1737 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); in at91_gpio_of_irq_setup()
1739 gpio_irqchip->name = "GPIO"; in at91_gpio_of_irq_setup()
1740 gpio_irqchip->irq_ack = gpio_irq_ack; in at91_gpio_of_irq_setup()
1741 gpio_irqchip->irq_disable = gpio_irq_mask; in at91_gpio_of_irq_setup()
1742 gpio_irqchip->irq_mask = gpio_irq_mask; in at91_gpio_of_irq_setup()
1743 gpio_irqchip->irq_unmask = gpio_irq_unmask; in at91_gpio_of_irq_setup()
1744 gpio_irqchip->irq_set_wake = gpio_irq_set_wake; in at91_gpio_of_irq_setup()
1745 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type; in at91_gpio_of_irq_setup()
1747 /* Disable irqs of this PIO controller */ in at91_gpio_of_irq_setup()
1748 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); in at91_gpio_of_irq_setup()
1755 girq = &at91_gpio->chip.irq; in at91_gpio_of_irq_setup()
1756 girq->chip = gpio_irqchip; in at91_gpio_of_irq_setup()
1757 girq->default_type = IRQ_TYPE_NONE; in at91_gpio_of_irq_setup()
1758 girq->handler = handle_edge_irq; in at91_gpio_of_irq_setup()
1765 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); in at91_gpio_of_irq_setup()
1767 girq->parent_handler = gpio_irq_handler; in at91_gpio_of_irq_setup()
1768 girq->num_parents = 1; in at91_gpio_of_irq_setup()
1769 girq->parents = devm_kcalloc(&pdev->dev, 1, in at91_gpio_of_irq_setup()
1770 sizeof(*girq->parents), in at91_gpio_of_irq_setup()
1772 if (!girq->parents) in at91_gpio_of_irq_setup()
1773 return -ENOMEM; in at91_gpio_of_irq_setup()
1774 girq->parents[0] = at91_gpio->pioc_virq; in at91_gpio_of_irq_setup()
1781 if (prev->next) { in at91_gpio_of_irq_setup()
1782 prev = prev->next; in at91_gpio_of_irq_setup()
1784 prev->next = at91_gpio; in at91_gpio_of_irq_setup()
1789 return -EINVAL; in at91_gpio_of_irq_setup()
1808 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1809 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1810 { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1816 struct device_node *np = pdev->dev.of_node; in at91_gpio_probe()
1828 ret = -EBUSY; in at91_gpio_probe()
1838 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); in at91_gpio_probe()
1840 ret = -ENOMEM; in at91_gpio_probe()
1844 at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0); in at91_gpio_probe()
1845 if (IS_ERR(at91_chip->regbase)) { in at91_gpio_probe()
1846 ret = PTR_ERR(at91_chip->regbase); in at91_gpio_probe()
1850 at91_chip->ops = (const struct at91_pinctrl_mux_ops *) in at91_gpio_probe()
1851 of_match_device(at91_gpio_of_match, &pdev->dev)->data; in at91_gpio_probe()
1852 at91_chip->pioc_virq = irq; in at91_gpio_probe()
1853 at91_chip->pioc_idx = alias_idx; in at91_gpio_probe()
1855 at91_chip->clock = devm_clk_get(&pdev->dev, NULL); in at91_gpio_probe()
1856 if (IS_ERR(at91_chip->clock)) { in at91_gpio_probe()
1857 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); in at91_gpio_probe()
1858 ret = PTR_ERR(at91_chip->clock); in at91_gpio_probe()
1862 ret = clk_prepare_enable(at91_chip->clock); in at91_gpio_probe()
1864 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n"); in at91_gpio_probe()
1868 at91_chip->chip = at91_gpio_template; in at91_gpio_probe()
1870 chip = &at91_chip->chip; in at91_gpio_probe()
1871 chip->of_node = np; in at91_gpio_probe()
1872 chip->label = dev_name(&pdev->dev); in at91_gpio_probe()
1873 chip->parent = &pdev->dev; in at91_gpio_probe()
1874 chip->owner = THIS_MODULE; in at91_gpio_probe()
1875 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; in at91_gpio_probe()
1877 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { in at91_gpio_probe()
1879 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", in at91_gpio_probe()
1882 chip->ngpio = ngpio; in at91_gpio_probe()
1885 names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *), in at91_gpio_probe()
1889 ret = -ENOMEM; in at91_gpio_probe()
1893 for (i = 0; i < chip->ngpio; i++) in at91_gpio_probe()
1894 names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); in at91_gpio_probe()
1896 chip->names = (const char *const *)names; in at91_gpio_probe()
1898 range = &at91_chip->range; in at91_gpio_probe()
1899 range->name = chip->label; in at91_gpio_probe()
1900 range->id = alias_idx; in at91_gpio_probe()
1901 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; in at91_gpio_probe()
1903 range->npins = chip->ngpio; in at91_gpio_probe()
1904 range->gc = chip; in at91_gpio_probe()
1917 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); in at91_gpio_probe()
1923 clk_disable_unprepare(at91_chip->clock); in at91_gpio_probe()
1925 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); in at91_gpio_probe()
1932 .name = "gpio-at91",
1940 .name = "pinctrl-at91",