42 	u32 pin_reg;  in amd_gpio_get_direction()  local
46 	pin_reg = readl(gpio_dev->base + offset * 4);  in amd_gpio_get_direction()
49 	if (pin_reg & BIT(OUTPUT_ENABLE_OFF))  in amd_gpio_get_direction()
58 	u32 pin_reg;  in amd_gpio_direction_input()  local
62 	pin_reg = readl(gpio_dev->base + offset * 4);  in amd_gpio_direction_input()
63 	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);  in amd_gpio_direction_input()
64 	writel(pin_reg, gpio_dev->base + offset * 4);  in amd_gpio_direction_input()
73 	u32 pin_reg;  in amd_gpio_direction_output()  local
78 	pin_reg = readl(gpio_dev->base + offset * 4);  in amd_gpio_direction_output()
79 	pin_reg |= BIT(OUTPUT_ENABLE_OFF);  in amd_gpio_direction_output()
81 		pin_reg |= BIT(OUTPUT_VALUE_OFF);  in amd_gpio_direction_output()
83 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);  in amd_gpio_direction_output()
84 	writel(pin_reg, gpio_dev->base + offset * 4);  in amd_gpio_direction_output()
92 	u32 pin_reg;  in amd_gpio_get_value()  local
97 	pin_reg = readl(gpio_dev->base + offset * 4);  in amd_gpio_get_value()
100 	return !!(pin_reg & BIT(PIN_STS_OFF));  in amd_gpio_get_value()
105 	u32 pin_reg;  in amd_gpio_set_value()  local
110 	pin_reg = readl(gpio_dev->base + offset * 4);  in amd_gpio_set_value()
112 		pin_reg |= BIT(OUTPUT_VALUE_OFF);  in amd_gpio_set_value()
114 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);  in amd_gpio_set_value()
115 	writel(pin_reg, gpio_dev->base + offset * 4);  in amd_gpio_set_value()
123 	u32 pin_reg;  in amd_gpio_set_debounce()  local
129 	pin_reg = readl(gpio_dev->base + offset * 4);  in amd_gpio_set_debounce()
132 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;  in amd_gpio_set_debounce()
133 		pin_reg &= ~DB_TMR_OUT_MASK;  in amd_gpio_set_debounce()
145 			pin_reg |= 1;  in amd_gpio_set_debounce()
146 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);  in amd_gpio_set_debounce()
147 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);  in amd_gpio_set_debounce()
150 			pin_reg |= time & DB_TMR_OUT_MASK;  in amd_gpio_set_debounce()
151 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);  in amd_gpio_set_debounce()
152 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);  in amd_gpio_set_debounce()
155 			pin_reg |= time & DB_TMR_OUT_MASK;  in amd_gpio_set_debounce()
156 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);  in amd_gpio_set_debounce()
157 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);  in amd_gpio_set_debounce()
160 			pin_reg |= time & DB_TMR_OUT_MASK;  in amd_gpio_set_debounce()
161 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);  in amd_gpio_set_debounce()
162 			pin_reg |= BIT(DB_TMR_LARGE_OFF);  in amd_gpio_set_debounce()
165 			pin_reg |= time & DB_TMR_OUT_MASK;  in amd_gpio_set_debounce()
166 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);  in amd_gpio_set_debounce()
167 			pin_reg |= BIT(DB_TMR_LARGE_OFF);  in amd_gpio_set_debounce()
169 			pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);  in amd_gpio_set_debounce()
173 		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);  in amd_gpio_set_debounce()
174 		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);  in amd_gpio_set_debounce()
175 		pin_reg &= ~DB_TMR_OUT_MASK;  in amd_gpio_set_debounce()
176 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);  in amd_gpio_set_debounce()
178 	writel(pin_reg, gpio_dev->base + offset * 4);  in amd_gpio_set_debounce()
199 	u32 pin_reg;  in amd_gpio_dbg_show()  local
253 			pin_reg = readl(gpio_dev->base + i * 4);  in amd_gpio_dbg_show()
256 			if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {  in amd_gpio_dbg_show()
257 				u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &  in amd_gpio_dbg_show()
265 				else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&  in amd_gpio_dbg_show()
271 				if (pin_reg & BIT(LEVEL_TRIG_OFF))  in amd_gpio_dbg_show()
283 			if (pin_reg & BIT(INTERRUPT_MASK_OFF))  in amd_gpio_dbg_show()
290 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))  in amd_gpio_dbg_show()
295 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))  in amd_gpio_dbg_show()
300 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))  in amd_gpio_dbg_show()
305 			if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {  in amd_gpio_dbg_show()
307 				if (pin_reg & BIT(PULL_UP_SEL_OFF))  in amd_gpio_dbg_show()
316 			if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))  in amd_gpio_dbg_show()
321 			if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {  in amd_gpio_dbg_show()
324 				if (pin_reg & BIT(OUTPUT_VALUE_OFF))  in amd_gpio_dbg_show()
332 				if (pin_reg & BIT(PIN_STS_OFF))  in amd_gpio_dbg_show()
338 			db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;  in amd_gpio_dbg_show()
340 				tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);  in amd_gpio_dbg_show()
341 				tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);  in amd_gpio_dbg_show()
342 				time = pin_reg & DB_TMR_OUT_MASK;  in amd_gpio_dbg_show()
375 				debounce_enable, debounce_value, pin_reg);  in amd_gpio_dbg_show()
385 	u32 pin_reg;  in amd_gpio_irq_enable()  local
391 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_enable()
392 	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);  in amd_gpio_irq_enable()
393 	pin_reg |= BIT(INTERRUPT_MASK_OFF);  in amd_gpio_irq_enable()
394 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_enable()
400 	u32 pin_reg;  in amd_gpio_irq_disable()  local
406 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_disable()
407 	pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);  in amd_gpio_irq_disable()
408 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);  in amd_gpio_irq_disable()
409 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_disable()
415 	u32 pin_reg;  in amd_gpio_irq_mask()  local
421 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_mask()
422 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);  in amd_gpio_irq_mask()
423 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_mask()
429 	u32 pin_reg;  in amd_gpio_irq_unmask()  local
435 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_unmask()
436 	pin_reg |= BIT(INTERRUPT_MASK_OFF);  in amd_gpio_irq_unmask()
437 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_unmask()
443 	u32 pin_reg;  in amd_gpio_irq_set_wake()  local
451 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_set_wake()
454 		pin_reg |= wake_mask;  in amd_gpio_irq_set_wake()
456 		pin_reg &= ~wake_mask;  in amd_gpio_irq_set_wake()
458 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_set_wake()
490 	u32 pin_reg, pin_reg_irq_en, mask;  in amd_gpio_irq_set_type()  local
496 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_set_type()
500 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);  in amd_gpio_irq_set_type()
501 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);  in amd_gpio_irq_set_type()
502 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;  in amd_gpio_irq_set_type()
507 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);  in amd_gpio_irq_set_type()
508 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);  in amd_gpio_irq_set_type()
509 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;  in amd_gpio_irq_set_type()
514 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);  in amd_gpio_irq_set_type()
515 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);  in amd_gpio_irq_set_type()
516 		pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;  in amd_gpio_irq_set_type()
521 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;  in amd_gpio_irq_set_type()
522 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);  in amd_gpio_irq_set_type()
523 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;  in amd_gpio_irq_set_type()
528 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;  in amd_gpio_irq_set_type()
529 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);  in amd_gpio_irq_set_type()
530 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;  in amd_gpio_irq_set_type()
542 	pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;  in amd_gpio_irq_set_type()
559 	pin_reg_irq_en = pin_reg;  in amd_gpio_irq_set_type()
565 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);  in amd_gpio_irq_set_type()
708 	u32 pin_reg;  in amd_pinconf_get()  local
715 	pin_reg = readl(gpio_dev->base + pin*4);  in amd_pinconf_get()
719 		arg = pin_reg & DB_TMR_OUT_MASK;  in amd_pinconf_get()
723 		arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);  in amd_pinconf_get()
727 		arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));  in amd_pinconf_get()
731 		arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;  in amd_pinconf_get()
751 	u32 pin_reg;  in amd_pinconf_set()  local
760 		pin_reg = readl(gpio_dev->base + pin*4);  in amd_pinconf_set()
764 			pin_reg &= ~DB_TMR_OUT_MASK;  in amd_pinconf_set()
765 			pin_reg |= arg & DB_TMR_OUT_MASK;  in amd_pinconf_set()
769 			pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);  in amd_pinconf_set()
770 			pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;  in amd_pinconf_set()
774 			pin_reg &= ~BIT(PULL_UP_SEL_OFF);  in amd_pinconf_set()
775 			pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;  in amd_pinconf_set()
776 			pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);  in amd_pinconf_set()
777 			pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;  in amd_pinconf_set()
781 			pin_reg &= ~(DRV_STRENGTH_SEL_MASK  in amd_pinconf_set()
783 			pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)  in amd_pinconf_set()
793 		writel(pin_reg, gpio_dev->base + pin*4);  in amd_pinconf_set()
847 	u32 pin_reg, mask;  in amd_gpio_irq_init()  local
863 		pin_reg = readl(gpio_dev->base + i * 4);  in amd_gpio_irq_init()
864 		pin_reg &= ~mask;  in amd_gpio_irq_init()
865 		writel(pin_reg, gpio_dev->base + i * 4);  in amd_gpio_irq_init()