1 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/pinctrl/pinconf-generic.h>
25 #include "pinctrl-intel.h"
98 #define pin_to_padno(c, p)	((p) - (c)->pin_base)
99 #define padgroup_offset(g, p)	((p) - (g)->base)
107 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_get_community()
108 		community = &pctrl->communities[i];  in intel_get_community()
109 		if (pin >= community->pin_base &&  in intel_get_community()
110 		    pin < community->pin_base + community->npins)  in intel_get_community()
114 	dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);  in intel_get_community()
124 	for (i = 0; i < community->ngpps; i++) {  in intel_community_get_padgroup()
125 		const struct intel_padgroup *padgrp = &community->gpps[i];  in intel_community_get_padgroup()
127 		if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)  in intel_community_get_padgroup()
146 	nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;  in intel_get_padcfg()
151 	return community->pad_regs + reg + padno * nregs * 4;  in intel_get_padcfg()
164 	if (!community->padown_offset)  in intel_pad_owned_by_host()
173 	offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;  in intel_pad_owned_by_host()
174 	padown = community->regs + offset;  in intel_pad_owned_by_host()
189 	if (!community->hostown_offset)  in intel_pad_acpi_mode()
197 	offset = community->hostown_offset + padgrp->reg_num * 4;  in intel_pad_acpi_mode()
198 	hostown = community->regs + offset;  in intel_pad_acpi_mode()
204  * enum - Locking variants of the pad configuration
207  * @PAD_LOCKED:		pad configuration registers, except TX state, are locked
208  * @PAD_LOCKED_TX:	pad configuration TX state is locked
209  * @PAD_LOCKED_FULL:	pad configuration registers are locked completely
211  * Locking is considered as read-only mode for corresponding registers and
212  * their respective fields. That said, TX state bit is locked separately from
233 	if (!community->padcfglock_offset)  in intel_pad_locked()
245 	 * either fully or partially locked.  in intel_pad_locked()
247 	offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;  in intel_pad_locked()
248 	value = readl(community->regs + offset);  in intel_pad_locked()
252 	offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;  in intel_pad_locked()
253 	value = readl(community->regs + offset);  in intel_pad_locked()
274 	return pctrl->soc->ngroups;  in intel_get_groups_count()
282 	return pctrl->soc->groups[group].name;  in intel_get_group_name()
290 	*pins = pctrl->soc->groups[group].pins;  in intel_get_group_pins()
291 	*npins = pctrl->soc->groups[group].npins;  in intel_get_group_pins()
301 	int locked;  in intel_pin_dbg_show()  local
325 	locked = intel_pad_locked(pctrl, pin);  in intel_pin_dbg_show()
328 	if (locked || acpi) {  in intel_pin_dbg_show()
330 		if (locked)  in intel_pin_dbg_show()
331 			seq_puts(s, "LOCKED");  in intel_pin_dbg_show()
332 		if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)  in intel_pin_dbg_show()
334 		else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)  in intel_pin_dbg_show()
337 		if (locked && acpi)  in intel_pin_dbg_show()
357 	return pctrl->soc->nfunctions;  in intel_get_functions_count()
365 	return pctrl->soc->functions[function].name;  in intel_get_function_name()
375 	*groups = pctrl->soc->functions[function].groups;  in intel_get_function_groups()
376 	*ngroups = pctrl->soc->functions[function].ngroups;  in intel_get_function_groups()
384 	const struct intel_pingroup *grp = &pctrl->soc->groups[group];  in intel_pinmux_set_mux()
388 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_pinmux_set_mux()
392 	 * before we can enable the mux for this group.  in intel_pinmux_set_mux()
394 	for (i = 0; i < grp->npins; i++) {  in intel_pinmux_set_mux()
395 		if (!intel_pad_usable(pctrl, grp->pins[i])) {  in intel_pinmux_set_mux()
396 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_pinmux_set_mux()
397 			return -EBUSY;  in intel_pinmux_set_mux()
401 	/* Now enable the mux setting for each pin in the group */  in intel_pinmux_set_mux()
402 	for (i = 0; i < grp->npins; i++) {  in intel_pinmux_set_mux()
406 		padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);  in intel_pinmux_set_mux()
411 		if (grp->modes)  in intel_pinmux_set_mux()
412 			value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;  in intel_pinmux_set_mux()
414 			value |= grp->mode << PADCFG0_PMODE_SHIFT;  in intel_pinmux_set_mux()
419 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_pinmux_set_mux()
475 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_gpio_request_enable()
478 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_request_enable()
479 		return -EBUSY;  in intel_gpio_request_enable()
483 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_request_enable()
494 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_request_enable()
503 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_request_enable()
518 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_gpio_set_direction()
520 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_set_direction()
545 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_config_get_pull()
547 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_config_get_pull()
554 			return -EINVAL;  in intel_config_get_pull()
559 			return -EINVAL;  in intel_config_get_pull()
580 			return -EINVAL;  in intel_config_get_pull()
584 			if (!(community->features & PINCTRL_FEATURE_1K_PD))  in intel_config_get_pull()
585 				return -EINVAL;  in intel_config_get_pull()
589 			if (!(community->features & PINCTRL_FEATURE_1K_PD))  in intel_config_get_pull()
590 				return -EINVAL;  in intel_config_get_pull()
604 		return -EINVAL;  in intel_config_get_pull()
620 		return -ENOTSUPP;  in intel_config_get_debounce()
622 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_config_get_debounce()
624 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_config_get_debounce()
626 		return -EINVAL;  in intel_config_get_debounce()
643 		return -ENOTSUPP;  in intel_config_get()
661 		return -ENOTSUPP;  in intel_config_get()
682 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_config_set_pull()
714 			ret = -EINVAL;  in intel_config_set_pull()
734 			if (!(community->features & PINCTRL_FEATURE_1K_PD)) {  in intel_config_set_pull()
735 				ret = -EINVAL;  in intel_config_set_pull()
741 			if (!(community->features & PINCTRL_FEATURE_1K_PD)) {  in intel_config_set_pull()
742 				ret = -EINVAL;  in intel_config_set_pull()
748 			ret = -EINVAL;  in intel_config_set_pull()
757 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_config_set_pull()
771 		return -ENOTSUPP;  in intel_config_set_debounce()
775 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_config_set_debounce()
789 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_config_set_debounce()
790 			return -EINVAL;  in intel_config_set_debounce()
802 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_config_set_debounce()
814 		return -ENOTSUPP;  in intel_config_set()
834 			return -ENOTSUPP;  in intel_config_set()
855  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
871 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_gpio_to_pin()
872 		const struct intel_community *comm = &pctrl->communities[i];  in intel_gpio_to_pin()
875 		for (j = 0; j < comm->ngpps; j++) {  in intel_gpio_to_pin()
876 			const struct intel_padgroup *pgrp = &comm->gpps[j];  in intel_gpio_to_pin()
878 			if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)  in intel_gpio_to_pin()
881 			if (offset >= pgrp->gpio_base &&  in intel_gpio_to_pin()
882 			    offset < pgrp->gpio_base + pgrp->size) {  in intel_gpio_to_pin()
885 				pin = pgrp->base + offset - pgrp->gpio_base;  in intel_gpio_to_pin()
896 	return -EINVAL;  in intel_gpio_to_pin()
900  * intel_pin_to_gpio() - Translate from pin number to GPIO offset
913 		return -EINVAL;  in intel_pin_to_gpio()
917 		return -EINVAL;  in intel_pin_to_gpio()
919 	return pin - padgrp->base + padgrp->gpio_base;  in intel_pin_to_gpio()
931 		return -EINVAL;  in intel_gpio_get()
935 		return -EINVAL;  in intel_gpio_get()
961 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_gpio_set()
968 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_set()
981 		return -EINVAL;  in intel_gpio_get_direction()
985 		return -EINVAL;  in intel_gpio_get_direction()
987 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_gpio_get_direction()
989 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_get_direction()
991 		return -EINVAL;  in intel_gpio_get_direction()
1001 	return pinctrl_gpio_direction_input(chip->base + offset);  in intel_gpio_direction_input()
1008 	return pinctrl_gpio_direction_output(chip->base + offset);  in intel_gpio_direction_output()
1035 		gpp = padgrp->reg_num;  in intel_gpio_irq_ack()
1037 		is_offset = community->is_offset + gpp * 4;  in intel_gpio_irq_ack()
1039 		raw_spin_lock(&pctrl->lock);  in intel_gpio_irq_ack()
1040 		writel(BIT(gpp_offset), community->regs + is_offset);  in intel_gpio_irq_ack()
1041 		raw_spin_unlock(&pctrl->lock);  in intel_gpio_irq_ack()
1060 		gpp = padgrp->reg_num;  in intel_gpio_irq_mask_unmask()
1063 		reg = community->regs + community->ie_offset + gpp * 4;  in intel_gpio_irq_mask_unmask()
1064 		is = community->regs + community->is_offset + gpp * 4;  in intel_gpio_irq_mask_unmask()
1066 		raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_gpio_irq_mask_unmask()
1077 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_irq_mask_unmask()
1102 		return -EINVAL;  in intel_gpio_irq_type()
1110 		dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);  in intel_gpio_irq_type()
1111 		return -EPERM;  in intel_gpio_irq_type()
1114 	raw_spin_lock_irqsave(&pctrl->lock, flags);  in intel_gpio_irq_type()
1146 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);  in intel_gpio_irq_type()
1158 		enable_irq_wake(pctrl->irq);  in intel_gpio_irq_wake()
1160 		disable_irq_wake(pctrl->irq);  in intel_gpio_irq_wake()
1162 	dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);  in intel_gpio_irq_wake()
1169 	struct gpio_chip *gc = &pctrl->chip;  in intel_gpio_community_irq_handler()
1173 	for (gpp = 0; gpp < community->ngpps; gpp++) {  in intel_gpio_community_irq_handler()
1174 		const struct intel_padgroup *padgrp = &community->gpps[gpp];  in intel_gpio_community_irq_handler()
1177 		raw_spin_lock(&pctrl->lock);  in intel_gpio_community_irq_handler()
1179 		pending = readl(community->regs + community->is_offset +  in intel_gpio_community_irq_handler()
1180 				padgrp->reg_num * 4);  in intel_gpio_community_irq_handler()
1181 		enabled = readl(community->regs + community->ie_offset +  in intel_gpio_community_irq_handler()
1182 				padgrp->reg_num * 4);  in intel_gpio_community_irq_handler()
1184 		raw_spin_unlock(&pctrl->lock);  in intel_gpio_community_irq_handler()
1189 		for_each_set_bit(gpp_offset, &pending, padgrp->size) {  in intel_gpio_community_irq_handler()
1192 			irq = irq_find_mapping(gc->irq.domain,  in intel_gpio_community_irq_handler()
1193 					       padgrp->gpio_base + gpp_offset);  in intel_gpio_community_irq_handler()
1211 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_gpio_irq()
1212 		community = &pctrl->communities[i];  in intel_gpio_irq()
1224 	for (i = 0; i < community->ngpps; i++) {  in intel_gpio_add_community_ranges()
1225 		const struct intel_padgroup *gpp = &community->gpps[i];  in intel_gpio_add_community_ranges()
1227 		if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)  in intel_gpio_add_community_ranges()
1230 		ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),  in intel_gpio_add_community_ranges()
1231 					     gpp->gpio_base, gpp->base,  in intel_gpio_add_community_ranges()
1232 					     gpp->size);  in intel_gpio_add_community_ranges()
1245 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_gpio_add_pin_ranges()
1246 		struct intel_community *community = &pctrl->communities[i];  in intel_gpio_add_pin_ranges()
1250 			dev_err(pctrl->dev, "failed to add GPIO pin range\n");  in intel_gpio_add_pin_ranges()
1264 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_gpio_ngpio()
1265 		community = &pctrl->communities[i];  in intel_gpio_ngpio()
1266 		for (j = 0; j < community->ngpps; j++) {  in intel_gpio_ngpio()
1267 			const struct intel_padgroup *gpp = &community->gpps[j];  in intel_gpio_ngpio()
1269 			if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)  in intel_gpio_ngpio()
1272 			if (gpp->gpio_base + gpp->size > ngpio)  in intel_gpio_ngpio()
1273 				ngpio = gpp->gpio_base + gpp->size;  in intel_gpio_ngpio()
1285 	pctrl->chip = intel_gpio_chip;  in intel_gpio_probe()
1288 	pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);  in intel_gpio_probe()
1289 	pctrl->chip.label = dev_name(pctrl->dev);  in intel_gpio_probe()
1290 	pctrl->chip.parent = pctrl->dev;  in intel_gpio_probe()
1291 	pctrl->chip.base = -1;  in intel_gpio_probe()
1292 	pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;  in intel_gpio_probe()
1293 	pctrl->irq = irq;  in intel_gpio_probe()
1296 	pctrl->irqchip.name = dev_name(pctrl->dev);  in intel_gpio_probe()
1297 	pctrl->irqchip.irq_ack = intel_gpio_irq_ack;  in intel_gpio_probe()
1298 	pctrl->irqchip.irq_mask = intel_gpio_irq_mask;  in intel_gpio_probe()
1299 	pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;  in intel_gpio_probe()
1300 	pctrl->irqchip.irq_set_type = intel_gpio_irq_type;  in intel_gpio_probe()
1301 	pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;  in intel_gpio_probe()
1302 	pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;  in intel_gpio_probe()
1308 	ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,  in intel_gpio_probe()
1310 			       dev_name(pctrl->dev), pctrl);  in intel_gpio_probe()
1312 		dev_err(pctrl->dev, "failed to request interrupt\n");  in intel_gpio_probe()
1316 	girq = &pctrl->chip.irq;  in intel_gpio_probe()
1317 	girq->chip = &pctrl->irqchip;  in intel_gpio_probe()
1319 	girq->parent_handler = NULL;  in intel_gpio_probe()
1320 	girq->num_parents = 0;  in intel_gpio_probe()
1321 	girq->default_type = IRQ_TYPE_NONE;  in intel_gpio_probe()
1322 	girq->handler = handle_bad_irq;  in intel_gpio_probe()
1324 	ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);  in intel_gpio_probe()
1326 		dev_err(pctrl->dev, "failed to register gpiochip\n");  in intel_gpio_probe()
1338 	size_t i, ngpps = community->ngpps;  in intel_pinctrl_add_padgroups_by_gpps()
1340 	gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);  in intel_pinctrl_add_padgroups_by_gpps()
1342 		return -ENOMEM;  in intel_pinctrl_add_padgroups_by_gpps()
1345 		gpps[i] = community->gpps[i];  in intel_pinctrl_add_padgroups_by_gpps()
1348 			return -EINVAL;  in intel_pinctrl_add_padgroups_by_gpps()
1368 	community->gpps = gpps;  in intel_pinctrl_add_padgroups_by_gpps()
1377 	unsigned int npins = community->npins;  in intel_pinctrl_add_padgroups_by_size()
1379 	size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);  in intel_pinctrl_add_padgroups_by_size()
1381 	if (community->gpp_size > 32)  in intel_pinctrl_add_padgroups_by_size()
1382 		return -EINVAL;  in intel_pinctrl_add_padgroups_by_size()
1384 	gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);  in intel_pinctrl_add_padgroups_by_size()
1386 		return -ENOMEM;  in intel_pinctrl_add_padgroups_by_size()
1389 		unsigned int gpp_size = community->gpp_size;  in intel_pinctrl_add_padgroups_by_size()
1392 		gpps[i].base = community->pin_base + i * gpp_size;  in intel_pinctrl_add_padgroups_by_size()
1394 		npins -= gpps[i].size;  in intel_pinctrl_add_padgroups_by_size()
1403 		if (community->gpp_num_padown_regs)  in intel_pinctrl_add_padgroups_by_size()
1404 			padown_num += community->gpp_num_padown_regs;  in intel_pinctrl_add_padgroups_by_size()
1409 	community->ngpps = ngpps;  in intel_pinctrl_add_padgroups_by_size()
1410 	community->gpps = gpps;  in intel_pinctrl_add_padgroups_by_size()
1418 	const struct intel_pinctrl_soc_data *soc = pctrl->soc;  in intel_pinctrl_pm_init()
1423 	pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);  in intel_pinctrl_pm_init()
1425 		return -ENOMEM;  in intel_pinctrl_pm_init()
1427 	communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,  in intel_pinctrl_pm_init()
1430 		return -ENOMEM;  in intel_pinctrl_pm_init()
1433 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_pinctrl_pm_init()
1434 		struct intel_community *community = &pctrl->communities[i];  in intel_pinctrl_pm_init()
1437 		intmask = devm_kcalloc(pctrl->dev, community->ngpps,  in intel_pinctrl_pm_init()
1440 			return -ENOMEM;  in intel_pinctrl_pm_init()
1444 		hostown = devm_kcalloc(pctrl->dev, community->ngpps,  in intel_pinctrl_pm_init()
1447 			return -ENOMEM;  in intel_pinctrl_pm_init()
1452 	pctrl->context.pads = pads;  in intel_pinctrl_pm_init()
1453 	pctrl->context.communities = communities;  in intel_pinctrl_pm_init()
1465 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);  in intel_pinctrl_probe()
1467 		return -ENOMEM;  in intel_pinctrl_probe()
1469 	pctrl->dev = &pdev->dev;  in intel_pinctrl_probe()
1470 	pctrl->soc = soc_data;  in intel_pinctrl_probe()
1471 	raw_spin_lock_init(&pctrl->lock);  in intel_pinctrl_probe()
1477 	pctrl->ncommunities = pctrl->soc->ncommunities;  in intel_pinctrl_probe()
1478 	pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,  in intel_pinctrl_probe()
1479 				  sizeof(*pctrl->communities), GFP_KERNEL);  in intel_pinctrl_probe()
1480 	if (!pctrl->communities)  in intel_pinctrl_probe()
1481 		return -ENOMEM;  in intel_pinctrl_probe()
1483 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_pinctrl_probe()
1484 		struct intel_community *community = &pctrl->communities[i];  in intel_pinctrl_probe()
1489 		*community = pctrl->soc->communities[i];  in intel_pinctrl_probe()
1491 		regs = devm_platform_ioremap_resource(pdev, community->barno);  in intel_pinctrl_probe()
1501 			return -ENODEV;  in intel_pinctrl_probe()
1503 			community->features |= PINCTRL_FEATURE_DEBOUNCE;  in intel_pinctrl_probe()
1504 			community->features |= PINCTRL_FEATURE_1K_PD;  in intel_pinctrl_probe()
1513 				community->features |= PINCTRL_FEATURE_GPIO_HW_INFO;  in intel_pinctrl_probe()
1516 				community->features |= PINCTRL_FEATURE_PWM;  in intel_pinctrl_probe()
1519 				community->features |= PINCTRL_FEATURE_BLINK;  in intel_pinctrl_probe()
1522 				community->features |= PINCTRL_FEATURE_EXP;  in intel_pinctrl_probe()
1530 		dev_dbg(&pdev->dev, "Community%d features: %#08x\n", i, community->features);  in intel_pinctrl_probe()
1535 		community->regs = regs;  in intel_pinctrl_probe()
1536 		community->pad_regs = regs + offset;  in intel_pinctrl_probe()
1538 		if (community->gpps)  in intel_pinctrl_probe()
1554 	pctrl->pctldesc = intel_pinctrl_desc;  in intel_pinctrl_probe()
1555 	pctrl->pctldesc.name = dev_name(&pdev->dev);  in intel_pinctrl_probe()
1556 	pctrl->pctldesc.pins = pctrl->soc->pins;  in intel_pinctrl_probe()
1557 	pctrl->pctldesc.npins = pctrl->soc->npins;  in intel_pinctrl_probe()
1559 	pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,  in intel_pinctrl_probe()
1561 	if (IS_ERR(pctrl->pctldev)) {  in intel_pinctrl_probe()
1562 		dev_err(&pdev->dev, "failed to register pinctrl driver\n");  in intel_pinctrl_probe()
1563 		return PTR_ERR(pctrl->pctldev);  in intel_pinctrl_probe()
1579 	data = device_get_match_data(&pdev->dev);  in intel_pinctrl_probe_by_hid()
1581 		return -ENODATA;  in intel_pinctrl_probe_by_hid()
1606 	adev = ACPI_COMPANION(&pdev->dev);  in intel_pinctrl_get_soc_data()
1608 		const void *match = device_get_match_data(&pdev->dev);  in intel_pinctrl_get_soc_data()
1612 			if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {  in intel_pinctrl_get_soc_data()
1622 			return ERR_PTR(-ENODEV);  in intel_pinctrl_get_soc_data()
1624 		table = (const struct intel_pinctrl_soc_data **)id->driver_data;  in intel_pinctrl_get_soc_data()
1625 		data = table[pdev->id];  in intel_pinctrl_get_soc_data()
1628 	return data ?: ERR_PTR(-ENODATA);  in intel_pinctrl_get_soc_data()
1635 	const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);  in intel_pinctrl_should_save()
1643 	 * BIOS during resume and those are not always locked down so leave  in intel_pinctrl_should_save()
1646 	if (pd->mux_owner || pd->gpio_owner ||  in intel_pinctrl_should_save()
1647 	    gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))  in intel_pinctrl_should_save()
1660 	pads = pctrl->context.pads;  in intel_pinctrl_suspend_noirq()
1661 	for (i = 0; i < pctrl->soc->npins; i++) {  in intel_pinctrl_suspend_noirq()
1662 		const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];  in intel_pinctrl_suspend_noirq()
1666 		if (!intel_pinctrl_should_save(pctrl, desc->number))  in intel_pinctrl_suspend_noirq()
1669 		val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));  in intel_pinctrl_suspend_noirq()
1671 		val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));  in intel_pinctrl_suspend_noirq()
1674 		padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);  in intel_pinctrl_suspend_noirq()
1679 	communities = pctrl->context.communities;  in intel_pinctrl_suspend_noirq()
1680 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_pinctrl_suspend_noirq()
1681 		struct intel_community *community = &pctrl->communities[i];  in intel_pinctrl_suspend_noirq()
1685 		base = community->regs + community->ie_offset;  in intel_pinctrl_suspend_noirq()
1686 		for (gpp = 0; gpp < community->ngpps; gpp++)  in intel_pinctrl_suspend_noirq()
1689 		base = community->regs + community->hostown_offset;  in intel_pinctrl_suspend_noirq()
1690 		for (gpp = 0; gpp < community->ngpps; gpp++)  in intel_pinctrl_suspend_noirq()
1702 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_gpio_irq_init()
1707 		community = &pctrl->communities[i];  in intel_gpio_irq_init()
1708 		base = community->regs;  in intel_gpio_irq_init()
1710 		for (gpp = 0; gpp < community->ngpps; gpp++) {  in intel_gpio_irq_init()
1712 			writel(0, base + community->ie_offset + gpp * 4);  in intel_gpio_irq_init()
1713 			writel(0xffff, base + community->is_offset + gpp * 4);  in intel_gpio_irq_init()
1735 	const struct intel_community *community = &pctrl->communities[c];  in intel_restore_hostown()
1736 	const struct intel_padgroup *padgrp = &community->gpps[gpp];  in intel_restore_hostown()
1737 	struct device *dev = pctrl->dev;  in intel_restore_hostown()
1742 	if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)  in intel_restore_hostown()
1745 	for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)  in intel_restore_hostown()
1757 	struct device *dev = pctrl->dev;  in intel_restore_intmask()
1770 	struct device *dev = pctrl->dev;  in intel_restore_padcfg()
1793 	pads = pctrl->context.pads;  in intel_pinctrl_resume_noirq()
1794 	for (i = 0; i < pctrl->soc->npins; i++) {  in intel_pinctrl_resume_noirq()
1795 		const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];  in intel_pinctrl_resume_noirq()
1797 		if (!intel_pinctrl_should_save(pctrl, desc->number))  in intel_pinctrl_resume_noirq()
1800 		intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);  in intel_pinctrl_resume_noirq()
1801 		intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);  in intel_pinctrl_resume_noirq()
1802 		intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);  in intel_pinctrl_resume_noirq()
1805 	communities = pctrl->context.communities;  in intel_pinctrl_resume_noirq()
1806 	for (i = 0; i < pctrl->ncommunities; i++) {  in intel_pinctrl_resume_noirq()
1807 		struct intel_community *community = &pctrl->communities[i];  in intel_pinctrl_resume_noirq()
1811 		base = community->regs + community->ie_offset;  in intel_pinctrl_resume_noirq()
1812 		for (gpp = 0; gpp < community->ngpps; gpp++)  in intel_pinctrl_resume_noirq()
1815 		base = community->regs + community->hostown_offset;  in intel_pinctrl_resume_noirq()
1816 		for (gpp = 0; gpp < community->ngpps; gpp++)  in intel_pinctrl_resume_noirq()