1 // SPDX-License-Identifier: GPL-2.0
3  * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5  * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
29  * Lane Registers
32 /* TX De-emphasis parameters */
46 #define L0_TXPMD_TM_45_OVER_DP_POST1	BIT(2)
137 #define PROT_BUS_WIDTH_SHIFT		2
151 #define XPSGTR_TYPE_SATA_0		2  /* SATA controller lane 0 */
152 #define XPSGTR_TYPE_SATA_1		3  /* SATA controller lane 1 */
153 #define XPSGTR_TYPE_PCIE_0		4  /* PCIe controller lane 0 */
154 #define XPSGTR_TYPE_PCIE_1		5  /* PCIe controller lane 1 */
155 #define XPSGTR_TYPE_PCIE_2		6  /* PCIe controller lane 2 */
156 #define XPSGTR_TYPE_PCIE_3		7  /* PCIe controller lane 3 */
157 #define XPSGTR_TYPE_DP_0		8  /* Display Port controller lane 0 */
158 #define XPSGTR_TYPE_DP_1		9  /* Display Port controller lane 1 */
161 #define XPSGTR_TYPE_SGMII2		12 /* Ethernet SGMII controller 2 */
170  * struct xpsgtr_ssc - structure to hold SSC settings for a lane
184  * struct xpsgtr_phy - representation of a lane
186  * @type: controller which uses this lane
187  * @lane: lane number
188  * @protocol: protocol in which the lane operates
196 	u8 lane;  member
204  * struct xpsgtr_dev - representation of a ZynMP GT device
256 	return readl(gtr_dev->serdes + reg);  in xpsgtr_read()
261 	writel(value, gtr_dev->serdes + reg);  in xpsgtr_write()
276 	void __iomem *addr = gtr_phy->dev->serdes  in xpsgtr_read_phy()
277 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_read_phy()
285 	void __iomem *addr = gtr_phy->dev->serdes  in xpsgtr_write_phy()
286 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_write_phy()
294 	void __iomem *addr = gtr_phy->dev->serdes  in xpsgtr_clr_set_phy()
295 			   + gtr_phy->lane * PHY_REG_OFFSET + reg;  in xpsgtr_clr_set_phy()
308 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;  in xpsgtr_wait_pll_lock()
312 	dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");  in xpsgtr_wait_pll_lock()
322 		if (--timeout == 0) {  in xpsgtr_wait_pll_lock()
323 			ret = -ETIMEDOUT;  in xpsgtr_wait_pll_lock()
330 	if (ret == -ETIMEDOUT)  in xpsgtr_wait_pll_lock()
331 		dev_err(gtr_dev->dev,  in xpsgtr_wait_pll_lock()
332 			"lane %u (type %u, protocol %u): PLL lock timeout\n",  in xpsgtr_wait_pll_lock()
333 			gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);  in xpsgtr_wait_pll_lock()
338 /* Configure PLL and spread-sprectrum clock. */
344 	ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];  in xpsgtr_configure_pll()
345 	step_size = ssc->step_size;  in xpsgtr_configure_pll()
347 	xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),  in xpsgtr_configure_pll()
348 		       PLL_FREQ_MASK, ssc->pll_ref_clk);  in xpsgtr_configure_pll()
350 	/* Enable lane clock sharing, if required */  in xpsgtr_configure_pll()
351 	if (gtr_phy->refclk != gtr_phy->lane) {  in xpsgtr_configure_pll()
353 		xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),  in xpsgtr_configure_pll()
354 			       L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);  in xpsgtr_configure_pll()
373 			   STEPS_0_MASK, ssc->steps & STEPS_0_MASK);  in xpsgtr_configure_pll()
378 			   (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);  in xpsgtr_configure_pll()
387 /* Configure the lane protocol. */
390 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;  in xpsgtr_lane_set_protocol()
391 	u8 protocol = gtr_phy->protocol;  in xpsgtr_lane_set_protocol()
393 	switch (gtr_phy->lane) {  in xpsgtr_lane_set_protocol()
401 	case 2:  in xpsgtr_lane_set_protocol()
409 		/* We already checked 0 <= lane <= 3 */  in xpsgtr_lane_set_protocol()
421 /* DP-specific initialization. */
434 /* SATA-specific initialization. */
437 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;  in xpsgtr_phy_init_sata()
441 	writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);  in xpsgtr_phy_init_sata()
444 /* SGMII-specific initialization. */
447 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;  in xpsgtr_phy_init_sgmii()
451 		     PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT));  in xpsgtr_phy_init_sgmii()
453 		     PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT));  in xpsgtr_phy_init_sgmii()
458 /* Configure TX de-emphasis and margining for DP. */
489 	 * except when gtr_phy->skip_phy_init is false (this happens when FPD is  in xpsgtr_phy_init_required()
490 	 * shutdown during suspend or when gt lane is changed from current one)  in xpsgtr_phy_init_required()
492 	if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)  in xpsgtr_phy_init_required()
505 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;  in xpsgtr_phy_tx_term_fix()
520 	 * we need to configure any lane ICM_CFG to valid protocol. This  in xpsgtr_phy_tx_term_fix()
528 	dev_dbg(gtr_dev->dev, "calibrating...\n");  in xpsgtr_phy_tx_term_fix()
536 		if (!--timeout) {  in xpsgtr_phy_tx_term_fix()
537 			dev_err(gtr_dev->dev, "calibration time out\n");  in xpsgtr_phy_tx_term_fix()
538 			return -ETIMEDOUT;  in xpsgtr_phy_tx_term_fix()
544 	dev_dbg(gtr_dev->dev, "calibration done\n");  in xpsgtr_phy_tx_term_fix()
555 	/* Writing NMOS register value [2:0] */  in xpsgtr_phy_tx_term_fix()
569 	struct xpsgtr_dev *gtr_dev = gtr_phy->dev;  in xpsgtr_phy_init()
572 	mutex_lock(&gtr_dev->gtr_mutex);  in xpsgtr_phy_init()
578 	if (gtr_dev->tx_term_fix) {  in xpsgtr_phy_init()
583 		gtr_dev->tx_term_fix = false;  in xpsgtr_phy_init()
590 	 * Configure the PLL, the lane protocol, and perform protocol-specific  in xpsgtr_phy_init()
596 	switch (gtr_phy->protocol) {  in xpsgtr_phy_init()
611 	mutex_unlock(&gtr_dev->gtr_mutex);  in xpsgtr_phy_init()
619 	gtr_phy->skip_phy_init = false;  in xpsgtr_phy_exit()
635 	 * lane 0 last.  in xpsgtr_phy_power_on()
637 	if (gtr_phy->protocol != ICM_PROTOCOL_DP ||  in xpsgtr_phy_power_on()
638 	    gtr_phy->type == XPSGTR_TYPE_DP_0)  in xpsgtr_phy_power_on()
648 	if (gtr_phy->protocol != ICM_PROTOCOL_DP)  in xpsgtr_phy_configure()
651 	xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);  in xpsgtr_phy_configure()
668 /* Set the lane type and protocol based on the PHY type and instance number. */
684 		gtr_phy->protocol = ICM_PROTOCOL_SATA;  in xpsgtr_set_lane_type()
695 		gtr_phy->protocol = ICM_PROTOCOL_USB;  in xpsgtr_set_lane_type()
706 		gtr_phy->protocol = ICM_PROTOCOL_DP;  in xpsgtr_set_lane_type()
719 		gtr_phy->protocol = ICM_PROTOCOL_PCIE;  in xpsgtr_set_lane_type()
732 		gtr_phy->protocol = ICM_PROTOCOL_SGMII;  in xpsgtr_set_lane_type()
736 		return -EINVAL;  in xpsgtr_set_lane_type()
740 		return -EINVAL;  in xpsgtr_set_lane_type()
742 	gtr_phy->type = phy_types[phy_instance];  in xpsgtr_set_lane_type()
773 	if (args->args_count != 4) {  in xpsgtr_xlate()
775 		return ERR_PTR(-EINVAL);  in xpsgtr_xlate()
779 	 * Get the PHY parameters from the OF arguments and derive the lane  in xpsgtr_xlate()
782 	phy_lane = args->args[0];  in xpsgtr_xlate()
783 	if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {  in xpsgtr_xlate()
784 		dev_err(dev, "Invalid lane number %u\n", phy_lane);  in xpsgtr_xlate()
785 		return ERR_PTR(-ENODEV);  in xpsgtr_xlate()
788 	gtr_phy = &gtr_dev->phys[phy_lane];  in xpsgtr_xlate()
789 	phy_type = args->args[1];  in xpsgtr_xlate()
790 	phy_instance = args->args[2];  in xpsgtr_xlate()
794 		dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");  in xpsgtr_xlate()
798 	refclk = args->args[3];  in xpsgtr_xlate()
799 	if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||  in xpsgtr_xlate()
800 	    !gtr_dev->refclk_sscs[refclk]) {  in xpsgtr_xlate()
802 		return ERR_PTR(-EINVAL);  in xpsgtr_xlate()
805 	gtr_phy->refclk = refclk;  in xpsgtr_xlate()
808 	 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type  in xpsgtr_xlate()
809 	 * is allowed to operate on the lane.  in xpsgtr_xlate()
812 		if (icm_matrix[phy_lane][i] == gtr_phy->type)  in xpsgtr_xlate()
813 			return gtr_phy->phy;  in xpsgtr_xlate()
816 	return ERR_PTR(-EINVAL);  in xpsgtr_xlate()
829 	gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);  in xpsgtr_suspend()
830 	gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);  in xpsgtr_suspend()
832 	for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++)  in xpsgtr_suspend()
833 		clk_disable_unprepare(gtr_dev->clk[i]);  in xpsgtr_suspend()
846 	for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++) {  in xpsgtr_resume()
847 		err = clk_prepare_enable(gtr_dev->clk[i]);  in xpsgtr_resume()
856 	if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)  in xpsgtr_resume()
860 	if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&  in xpsgtr_resume()
861 	    icm_cfg1 == gtr_dev->saved_icm_cfg1)  in xpsgtr_resume()
867 	for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)  in xpsgtr_resume()
868 		gtr_dev->phys[i].skip_phy_init = skip_phy_init;  in xpsgtr_resume()
873 	while (i--)  in xpsgtr_resume()
874 		clk_disable_unprepare(gtr_dev->clk[i]);  in xpsgtr_resume()
892 	for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) {  in xpsgtr_get_ref_clocks()
899 		clk = devm_clk_get_optional(gtr_dev->dev, name);  in xpsgtr_get_ref_clocks()
901 			ret = dev_err_probe(gtr_dev->dev, PTR_ERR(clk),  in xpsgtr_get_ref_clocks()
914 		gtr_dev->clk[refclk] = clk;  in xpsgtr_get_ref_clocks()
924 				gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];  in xpsgtr_get_ref_clocks()
930 			dev_err(gtr_dev->dev,  in xpsgtr_get_ref_clocks()
933 			ret = -EINVAL;  in xpsgtr_get_ref_clocks()
941 	while (refclk--)  in xpsgtr_get_ref_clocks()
942 		clk_disable_unprepare(gtr_dev->clk[refclk]);  in xpsgtr_get_ref_clocks()
949 	struct device_node *np = pdev->dev.of_node;  in xpsgtr_probe()
956 	gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);  in xpsgtr_probe()
958 		return -ENOMEM;  in xpsgtr_probe()
960 	gtr_dev->dev = &pdev->dev;  in xpsgtr_probe()
963 	mutex_init(&gtr_dev->gtr_mutex);  in xpsgtr_probe()
965 	if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))  in xpsgtr_probe()
966 		gtr_dev->tx_term_fix =  in xpsgtr_probe()
967 			of_property_read_bool(np, "xlnx,tx-termination-fix");  in xpsgtr_probe()
970 	gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");  in xpsgtr_probe()
971 	if (IS_ERR(gtr_dev->serdes))  in xpsgtr_probe()
972 		return PTR_ERR(gtr_dev->serdes);  in xpsgtr_probe()
974 	gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");  in xpsgtr_probe()
975 	if (IS_ERR(gtr_dev->siou))  in xpsgtr_probe()
976 		return PTR_ERR(gtr_dev->siou);  in xpsgtr_probe()
983 	for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {  in xpsgtr_probe()
984 		struct xpsgtr_phy *gtr_phy = &gtr_dev->phys[port];  in xpsgtr_probe()
987 		gtr_phy->lane = port;  in xpsgtr_probe()
988 		gtr_phy->dev = gtr_dev;  in xpsgtr_probe()
990 		phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);  in xpsgtr_probe()
992 			dev_err(&pdev->dev, "failed to create PHY\n");  in xpsgtr_probe()
997 		gtr_phy->phy = phy;  in xpsgtr_probe()
1002 	provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);  in xpsgtr_probe()
1004 		dev_err(&pdev->dev, "registering provider failed\n");  in xpsgtr_probe()
1011 	for (i = 0; i < ARRAY_SIZE(gtr_dev->clk); i++)  in xpsgtr_probe()
1012 		clk_disable_unprepare(gtr_dev->clk[i]);  in xpsgtr_probe()
1018 	{ .compatible = "xlnx,zynqmp-psgtr", },
1019 	{ .compatible = "xlnx,zynqmp-psgtr-v1.1", },
1027 		.name = "xilinx-psgtr",