Lines Matching refs:regmap_field

151 	struct regmap_field	*field;
160 	struct regmap_field	*field;
181 	struct regmap_field	*phy_en_refclk;
264 	struct regmap_field	*por_en;
265 	struct regmap_field	*phy_reset_n;
266 	struct regmap_field	*phy_en_refclk;
267 	struct regmap_field	*p_enable[WIZ_MAX_LANES];
268 	struct regmap_field	*p_align[WIZ_MAX_LANES];
269 	struct regmap_field	*p_raw_auto_start[WIZ_MAX_LANES];
270 	struct regmap_field	*p_standard_mode[WIZ_MAX_LANES];
271 	struct regmap_field	*p_mac_div_sel0[WIZ_MAX_LANES];
272 	struct regmap_field	*p_mac_div_sel1[WIZ_MAX_LANES];
273 	struct regmap_field	*p0_fullrt_div[WIZ_MAX_LANES];
274 	struct regmap_field	*pma_cmn_refclk_int_mode;
275 	struct regmap_field	*pma_cmn_refclk_mode;
276 	struct regmap_field	*pma_cmn_refclk_dig_div;
277 	struct regmap_field	*pma_cmn_refclk1_dig_div;
278 	struct regmap_field	*mux_sel_field[WIZ_MUX_NUM_CLOCKS];
279 	struct regmap_field	*div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
280 	struct regmap_field	*typec_ln10_swap;
558 	struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;  in wiz_phy_en_refclk_enable()
568 	struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;  in wiz_phy_en_refclk_disable()
576 	struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;  in wiz_phy_en_refclk_is_enabled()
622 	struct regmap_field *field = mux->field;  in wiz_clk_mux_get_parent()
632 	struct regmap_field *field = mux->field;  in wiz_clk_mux_set_parent()
644 static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,  in wiz_mux_clk_register()
706 				   struct regmap_field *field, const u32 *table)  in wiz_mux_of_clk_register()
764 	struct regmap_field *field = div->field;  in wiz_clk_div_recalc_rate()
784 	struct regmap_field *field = div->field;  in wiz_clk_div_set_rate()
801 				struct regmap_field *field,  in wiz_div_clk_register()