Lines Matching full:usb2

286 	struct tegra_xusb_usb2_lane *usb2;  in tegra186_usb2_lane_probe()  local
289 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); in tegra186_usb2_lane_probe()
290 if (!usb2) in tegra186_usb2_lane_probe()
293 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
294 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
295 usb2->base.index = index; in tegra186_usb2_lane_probe()
296 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
297 usb2->base.np = np; in tegra186_usb2_lane_probe()
299 err = tegra_xusb_lane_parse_dt(&usb2->base, np); in tegra186_usb2_lane_probe()
301 kfree(usb2); in tegra186_usb2_lane_probe()
305 return &usb2->base; in tegra186_usb2_lane_probe()
310 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_usb2_lane_remove() local
312 kfree(usb2); in tegra186_usb2_lane_remove()
394 * as well as capture the configuration of the USB2.0 pad in tegra186_utmi_enable_phy_sleepwalk()
438 /* switch the electric control of the USB2.0 pad to XUSB_AO */ in tegra186_utmi_enable_phy_sleepwalk()
474 /* switch the electric control of the USB2.0 pad to XUSB vcore logic */ in tegra186_utmi_disable_phy_sleepwalk()
591 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err); in tegra186_utmi_bias_pad_power_on()
655 dev_err(dev, "no port found for USB2 lane %u\n", index); in tegra_phy_xusb_utmi_pad_power_on()
789 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra186_utmi_phy_power_on() local
799 dev_err(dev, "no port found for USB2 lane %u\n", index); in tegra186_utmi_phy_power_on()
827 if (usb2->hs_curr_level_offset) { in tegra186_utmi_phy_power_on()
831 usb2->hs_curr_level_offset; in tegra186_utmi_phy_power_on()
876 dev_err(dev, "no port found for USB2 lane %u\n", index); in tegra186_utmi_phy_init()
903 dev_err(dev, "no port found for USB2 lane %u\n", index); in tegra186_utmi_phy_exit()
934 struct tegra_xusb_usb2_pad *usb2; in tegra186_usb2_pad_probe() local
938 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL); in tegra186_usb2_pad_probe()
939 if (!usb2) in tegra186_usb2_pad_probe()
942 pad = &usb2->base; in tegra186_usb2_pad_probe()
948 kfree(usb2); in tegra186_usb2_pad_probe()
955 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err); in tegra186_usb2_pad_probe()
975 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); in tegra186_usb2_pad_remove() local
977 kfree(usb2); in tegra186_usb2_pad_remove()
1001 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); in tegra186_usb2_port_map()
1196 struct tegra_xusb_usb2_port *usb2; in tegra186_usb3_phy_power_on() local
1207 usb2 = tegra_xusb_find_usb2_port(padctl, port->port); in tegra186_usb3_phy_power_on()
1208 if (!usb2) { in tegra186_usb3_phy_power_on()
1219 if (usb2->mode == USB_DR_MODE_UNKNOWN) in tegra186_usb3_phy_power_on()
1221 else if (usb2->mode == USB_DR_MODE_PERIPHERAL) in tegra186_usb3_phy_power_on()
1223 else if (usb2->mode == USB_DR_MODE_HOST) in tegra186_usb3_phy_power_on()
1225 else if (usb2->mode == USB_DR_MODE_OTG) in tegra186_usb3_phy_power_on()
1355 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad); in tegra186_usb3_pad_remove() local
1357 kfree(usb2); in tegra186_usb3_pad_remove()
1377 count = padctl->base.soc->ports.usb2.count; in tegra186_xusb_read_fuse_calibration()
1500 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1501 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1502 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1506 .name = "usb2",
1537 .usb2 = {
1566 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1567 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1568 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1569 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1573 .name = "usb2",
1602 .usb2 = {