Lines Matching +full:0 +full:x042
10 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728
11 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
12 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
15 PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50)
19 PHY_COMN_REG_CFG(0x023, 0x80, PWR_MODE_ANY),
20 PHY_COMN_REG_CFG(0x01d, 0x10, PWR_MODE_ANY),
22 PHY_TRSV_REG_CFG_AUTOV9(0x044, 0xb5, PWR_MODE_ANY),
23 PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x43, PWR_MODE_ANY),
24 PHY_TRSV_REG_CFG_AUTOV9(0x05b, 0x20, PWR_MODE_ANY),
25 PHY_TRSV_REG_CFG_AUTOV9(0x05e, 0xc0, PWR_MODE_ANY),
26 PHY_TRSV_REG_CFG_AUTOV9(0x038, 0x12, PWR_MODE_ANY),
27 PHY_TRSV_REG_CFG_AUTOV9(0x059, 0x58, PWR_MODE_ANY),
28 PHY_TRSV_REG_CFG_AUTOV9(0x06c, 0x18, PWR_MODE_ANY),
29 PHY_TRSV_REG_CFG_AUTOV9(0x06d, 0x02, PWR_MODE_ANY),
31 PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
32 PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),
34 PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
35 PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
42 PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
43 PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
44 PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
46 PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
47 PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
49 PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
66 .has_symbol_clk = 0,