382 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)  in inno_write()  function
434 		inno_write(inno, 0x04, intr_stat1);  in inno_hdmi_phy_rk3328_hardirq()
436 		inno_write(inno, 0x06, intr_stat2);  in inno_hdmi_phy_rk3328_hardirq()
438 		inno_write(inno, 0x08, intr_stat3);  in inno_hdmi_phy_rk3328_hardirq()
645 	inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_clk_set_rate()
795 	inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));  in inno_hdmi_phy_rk3328_clk_set_rate()
800 	inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);  in inno_hdmi_phy_rk3328_clk_set_rate()
801 	inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3328_clk_set_rate()
802 	inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) |  in inno_hdmi_phy_rk3328_clk_set_rate()
804 	inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |  in inno_hdmi_phy_rk3328_clk_set_rate()
806 	inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |  in inno_hdmi_phy_rk3328_clk_set_rate()
809 	inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));  in inno_hdmi_phy_rk3328_clk_set_rate()
810 	inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));  in inno_hdmi_phy_rk3328_clk_set_rate()
811 	inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));  in inno_hdmi_phy_rk3328_clk_set_rate()
880 	inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN |  in inno_hdmi_phy_rk3228_init()
915 	inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_power_on()
930 		inno_write(inno, 0xef + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3228_power_on()
978 	inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN |  in inno_hdmi_phy_rk3328_init()
981 	inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN |  in inno_hdmi_phy_rk3328_init()
985 	inno_write(inno, 0x05, 0);  in inno_hdmi_phy_rk3328_init()
986 	inno_write(inno, 0x07, 0);  in inno_hdmi_phy_rk3328_init()
1022 	inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3328_power_on()
1024 		inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS);  in inno_hdmi_phy_rk3328_power_on()
1025 		inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |  in inno_hdmi_phy_rk3328_power_on()
1030 		inno_write(inno, 0xad, v);  in inno_hdmi_phy_rk3328_power_on()
1031 		inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |  in inno_hdmi_phy_rk3328_power_on()
1033 		inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |  in inno_hdmi_phy_rk3328_power_on()
1038 		inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);  in inno_hdmi_phy_rk3328_power_on()
1048 		inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v)  in inno_hdmi_phy_rk3328_power_on()
1050 		inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v));  in inno_hdmi_phy_rk3328_power_on()
1051 		inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100);  in inno_hdmi_phy_rk3328_power_on()
1055 		inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB);  in inno_hdmi_phy_rk3328_power_on()
1091 	inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET)  in inno_hdmi_phy_rk3328_power_on()
1093 	inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET)  in inno_hdmi_phy_rk3328_power_on()
1106 	inno_write(inno, 0x05, 0);  in inno_hdmi_phy_rk3328_power_off()
1107 	inno_write(inno, 0x07, 0);  in inno_hdmi_phy_rk3328_power_off()