2939 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)  in qphy_setbits()  function
4057 		qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],  in qcom_qmp_phy_serdes_init()
4597 		qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,  in qcom_qmp_phy_com_init()
4600 		qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,  in qcom_qmp_phy_com_init()
4605 		qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);  in qcom_qmp_phy_com_init()
4607 		qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,  in qcom_qmp_phy_com_init()
4620 		qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],  in qcom_qmp_phy_com_init()
4624 			qphy_setbits(pcs,  in qcom_qmp_phy_com_init()
4628 			qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,  in qcom_qmp_phy_com_init()
4662 		qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],  in qcom_qmp_phy_com_exit()
4666 		qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],  in qcom_qmp_phy_com_exit()
4818 		qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);  in qcom_qmp_phy_power_on()
4828 		qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);  in qcom_qmp_phy_power_on()
4871 			qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);  in qcom_qmp_phy_power_off()
4951 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);  in qcom_qmp_phy_enable_autonomous_mode()
4959 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);  in qcom_qmp_phy_enable_autonomous_mode()
4974 		qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);  in qcom_qmp_phy_disable_autonomous_mode()
4979 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);  in qcom_qmp_phy_disable_autonomous_mode()