Lines Matching refs:pcs
2878 void __iomem *pcs; member
4079 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
4086 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
4092 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v3_phy_dp_aux_init()
4100 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v3_phy_dp_aux_init()
4101 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_phy_dp_aux_init()
4102 writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v3_phy_dp_aux_init()
4103 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); in qcom_qmp_v3_phy_dp_aux_init()
4104 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); in qcom_qmp_v3_phy_dp_aux_init()
4105 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); in qcom_qmp_v3_phy_dp_aux_init()
4106 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); in qcom_qmp_v3_phy_dp_aux_init()
4107 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); in qcom_qmp_v3_phy_dp_aux_init()
4108 writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); in qcom_qmp_v3_phy_dp_aux_init()
4109 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); in qcom_qmp_v3_phy_dp_aux_init()
4115 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); in qcom_qmp_v3_phy_dp_aux_init()
4230 writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_phy_configure_dp_mode()
4232 writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE); in qcom_qmp_phy_configure_dp_mode()
4246 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); in qcom_qmp_v3_phy_configure_dp_phy()
4247 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); in qcom_qmp_v3_phy_configure_dp_phy()
4270 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV); in qcom_qmp_v3_phy_configure_dp_phy()
4275 writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v3_phy_configure_dp_phy()
4276 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
4277 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
4278 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
4279 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
4290 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
4292 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
4299 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
4301 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v3_phy_configure_dp_phy()
4303 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS, in qcom_qmp_v3_phy_configure_dp_phy()
4323 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v3_dp_phy_calibrate()
4332 qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_v4_phy_dp_aux_init()
4337 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0); in qcom_qmp_v4_phy_dp_aux_init()
4338 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_phy_dp_aux_init()
4339 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v4_phy_dp_aux_init()
4340 writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3); in qcom_qmp_v4_phy_dp_aux_init()
4341 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4); in qcom_qmp_v4_phy_dp_aux_init()
4342 writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5); in qcom_qmp_v4_phy_dp_aux_init()
4343 writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6); in qcom_qmp_v4_phy_dp_aux_init()
4344 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7); in qcom_qmp_v4_phy_dp_aux_init()
4345 writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8); in qcom_qmp_v4_phy_dp_aux_init()
4346 writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9); in qcom_qmp_v4_phy_dp_aux_init()
4352 qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); in qcom_qmp_v4_phy_dp_aux_init()
4378 writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1); in qcom_qmp_v4_phy_configure_dp_phy()
4382 writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_phy_configure_dp_phy()
4383 writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2); in qcom_qmp_v4_phy_configure_dp_phy()
4385 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); in qcom_qmp_v4_phy_configure_dp_phy()
4386 writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); in qcom_qmp_v4_phy_configure_dp_phy()
4409 writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV); in qcom_qmp_v4_phy_configure_dp_phy()
4414 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
4415 writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
4416 writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
4417 writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
4442 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
4444 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v4_phy_configure_dp_phy()
4451 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v4_phy_configure_dp_phy()
4485 writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
4487 writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG); in qcom_qmp_v4_phy_configure_dp_phy()
4489 if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS, in qcom_qmp_v4_phy_configure_dp_phy()
4521 writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1); in qcom_qmp_v4_dp_phy_calibrate()
4557 void __iomem *pcs = qphy->pcs; in qcom_qmp_phy_com_init() local
4624 qphy_setbits(pcs, in qcom_qmp_phy_com_init()
4628 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, in qcom_qmp_phy_com_init()
4734 void __iomem *pcs = qphy->pcs; in qcom_qmp_phy_power_on() local
4797 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num); in qcom_qmp_phy_power_on()
4799 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec, in qcom_qmp_phy_power_on()
4818 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); in qcom_qmp_phy_power_on()
4826 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qcom_qmp_phy_power_on()
4828 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qcom_qmp_phy_power_on()
4831 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; in qcom_qmp_phy_power_on()
4835 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qcom_qmp_phy_power_on()
4867 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL); in qcom_qmp_phy_power_off()
4871 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qcom_qmp_phy_power_off()
4874 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); in qcom_qmp_phy_power_off()
4878 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qcom_qmp_phy_power_off()
4881 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL, in qcom_qmp_phy_power_off()
4940 void __iomem *pcs = qphy->pcs; in qcom_qmp_phy_enable_autonomous_mode() local
4951 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qcom_qmp_phy_enable_autonomous_mode()
4953 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qcom_qmp_phy_enable_autonomous_mode()
4955 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], in qcom_qmp_phy_enable_autonomous_mode()
4959 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); in qcom_qmp_phy_enable_autonomous_mode()
4969 void __iomem *pcs = qphy->pcs; in qcom_qmp_phy_disable_autonomous_mode() local
4976 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], in qcom_qmp_phy_disable_autonomous_mode()
4979 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qcom_qmp_phy_disable_autonomous_mode()
4981 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); in qcom_qmp_phy_disable_autonomous_mode()
5416 qphy->pcs = of_iomap(np, 2); in qcom_qmp_phy_create()
5417 if (!qphy->pcs) in qcom_qmp_phy_create()