1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
101 	/* u2 eye diagram */
119 	void __iomem *pbase = inst->port_base;  in u2_phy_slew_rate_calibrate()
125 	if (inst->eye_src)  in u2_phy_slew_rate_calibrate()
168 		tmp = xsphy->src_ref_clk * xsphy->src_coef;  in u2_phy_slew_rate_calibrate()
175 	dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",  in u2_phy_slew_rate_calibrate()
176 		inst->index, fm_out, calib_val,  in u2_phy_slew_rate_calibrate()
177 		xsphy->src_ref_clk, xsphy->src_coef);  in u2_phy_slew_rate_calibrate()
194 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_init()
210 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_power_on()
211 	u32 index = inst->index;  in u2_phy_instance_power_on()
223 	dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_on()
229 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_power_off()
230 	u32 index = inst->index;  in u2_phy_instance_power_off()
242 	dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_off()
251 	tmp = readl(inst->port_base + XSP_U2PHYDTM1);  in u2_phy_instance_set_mode()
266 	writel(tmp, inst->port_base + XSP_U2PHYDTM1);  in u2_phy_instance_set_mode()
272 	struct device *dev = &inst->phy->dev;  in phy_parse_property()
274 	switch (inst->type) {  in phy_parse_property()
276 		device_property_read_u32(dev, "mediatek,efuse-intr",  in phy_parse_property()
277 					 &inst->efuse_intr);  in phy_parse_property()
278 		device_property_read_u32(dev, "mediatek,eye-src",  in phy_parse_property()
279 					 &inst->eye_src);  in phy_parse_property()
280 		device_property_read_u32(dev, "mediatek,eye-vrt",  in phy_parse_property()
281 					 &inst->eye_vrt);  in phy_parse_property()
282 		device_property_read_u32(dev, "mediatek,eye-term",  in phy_parse_property()
283 					 &inst->eye_term);  in phy_parse_property()
284 		dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",  in phy_parse_property()
285 			inst->efuse_intr, inst->eye_src,  in phy_parse_property()
286 			inst->eye_vrt, inst->eye_term);  in phy_parse_property()
289 		device_property_read_u32(dev, "mediatek,efuse-intr",  in phy_parse_property()
290 					 &inst->efuse_intr);  in phy_parse_property()
291 		device_property_read_u32(dev, "mediatek,efuse-tx-imp",  in phy_parse_property()
292 					 &inst->efuse_tx_imp);  in phy_parse_property()
293 		device_property_read_u32(dev, "mediatek,efuse-rx-imp",  in phy_parse_property()
294 					 &inst->efuse_rx_imp);  in phy_parse_property()
295 		dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",  in phy_parse_property()
296 			inst->efuse_intr, inst->efuse_tx_imp,  in phy_parse_property()
297 			inst->efuse_rx_imp);  in phy_parse_property()
300 		dev_err(xsphy->dev, "incompatible phy type\n");  in phy_parse_property()
308 	void __iomem *pbase = inst->port_base;  in u2_phy_props_set()
311 	if (inst->efuse_intr) {  in u2_phy_props_set()
314 		tmp |= P2A1_RG_INTR_CAL_VAL(inst->efuse_intr);  in u2_phy_props_set()
318 	if (inst->eye_src) {  in u2_phy_props_set()
321 		tmp |= P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src);  in u2_phy_props_set()
325 	if (inst->eye_vrt) {  in u2_phy_props_set()
328 		tmp |= P2A1_RG_VRT_SEL_VAL(inst->eye_vrt);  in u2_phy_props_set()
332 	if (inst->eye_term) {  in u2_phy_props_set()
335 		tmp |= P2A1_RG_TERM_SEL_VAL(inst->eye_term);  in u2_phy_props_set()
343 	void __iomem *pbase = inst->port_base;  in u3_phy_props_set()
346 	if (inst->efuse_intr) {  in u3_phy_props_set()
347 		tmp = readl(xsphy->glb_base + SSPXTP_PHYA_GLB_00);  in u3_phy_props_set()
349 		tmp |= RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr);  in u3_phy_props_set()
350 		writel(tmp, xsphy->glb_base + SSPXTP_PHYA_GLB_00);  in u3_phy_props_set()
353 	if (inst->efuse_tx_imp) {  in u3_phy_props_set()
356 		tmp |= RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp);  in u3_phy_props_set()
360 	if (inst->efuse_rx_imp) {  in u3_phy_props_set()
363 		tmp |= RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp);  in u3_phy_props_set()
371 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_init()
374 	ret = clk_prepare_enable(inst->ref_clk);  in mtk_phy_init()
376 		dev_err(xsphy->dev, "failed to enable ref_clk\n");  in mtk_phy_init()
380 	switch (inst->type) {  in mtk_phy_init()
389 		dev_err(xsphy->dev, "incompatible phy type\n");  in mtk_phy_init()
390 		clk_disable_unprepare(inst->ref_clk);  in mtk_phy_init()
391 		return -EINVAL;  in mtk_phy_init()
400 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_on()
402 	if (inst->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
413 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_off()
415 	if (inst->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
425 	clk_disable_unprepare(inst->ref_clk);  in mtk_phy_exit()
432 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_set_mode()
434 	if (inst->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
445 	struct device_node *phy_np = args->np;  in mtk_phy_xlate()
448 	if (args->args_count != 1) {  in mtk_phy_xlate()
450 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
453 	for (index = 0; index < xsphy->nphys; index++)  in mtk_phy_xlate()
454 		if (phy_np == xsphy->phys[index]->phy->dev.of_node) {  in mtk_phy_xlate()
455 			inst = xsphy->phys[index];  in mtk_phy_xlate()
461 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
464 	inst->type = args->args[0];  in mtk_phy_xlate()
465 	if (!(inst->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
466 	      inst->type == PHY_TYPE_USB3)) {  in mtk_phy_xlate()
467 		dev_err(dev, "unsupported phy type: %d\n", inst->type);  in mtk_phy_xlate()
468 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
473 	return inst->phy;  in mtk_phy_xlate()
493 	struct device *dev = &pdev->dev;  in mtk_xsphy_probe()
494 	struct device_node *np = dev->of_node;  in mtk_xsphy_probe()
504 		return -ENOMEM;  in mtk_xsphy_probe()
506 	xsphy->nphys = of_get_child_count(np);  in mtk_xsphy_probe()
507 	xsphy->phys = devm_kcalloc(dev, xsphy->nphys,  in mtk_xsphy_probe()
508 				       sizeof(*xsphy->phys), GFP_KERNEL);  in mtk_xsphy_probe()
509 	if (!xsphy->phys)  in mtk_xsphy_probe()
510 		return -ENOMEM;  in mtk_xsphy_probe()
512 	xsphy->dev = dev;  in mtk_xsphy_probe()
519 		xsphy->glb_base = devm_ioremap_resource(dev, glb_res);  in mtk_xsphy_probe()
520 		if (IS_ERR(xsphy->glb_base)) {  in mtk_xsphy_probe()
522 			return PTR_ERR(xsphy->glb_base);  in mtk_xsphy_probe()
526 	xsphy->src_ref_clk = XSP_REF_CLK;  in mtk_xsphy_probe()
527 	xsphy->src_coef = XSP_SLEW_RATE_COEF;  in mtk_xsphy_probe()
529 	device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",  in mtk_xsphy_probe()
530 				 &xsphy->src_ref_clk);  in mtk_xsphy_probe()
531 	device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);  in mtk_xsphy_probe()
540 			retval = -ENOMEM;  in mtk_xsphy_probe()
544 		xsphy->phys[port] = inst;  in mtk_xsphy_probe()
555 			dev_err(dev, "failed to get address resource(id-%d)\n",  in mtk_xsphy_probe()
560 		inst->port_base = devm_ioremap_resource(&phy->dev, &res);  in mtk_xsphy_probe()
561 		if (IS_ERR(inst->port_base)) {  in mtk_xsphy_probe()
563 			retval = PTR_ERR(inst->port_base);  in mtk_xsphy_probe()
567 		inst->phy = phy;  in mtk_xsphy_probe()
568 		inst->index = port;  in mtk_xsphy_probe()
572 		inst->ref_clk = devm_clk_get(&phy->dev, "ref");  in mtk_xsphy_probe()
573 		if (IS_ERR(inst->ref_clk)) {  in mtk_xsphy_probe()
574 			dev_err(dev, "failed to get ref_clk(id-%d)\n", port);  in mtk_xsphy_probe()
575 			retval = PTR_ERR(inst->ref_clk);  in mtk_xsphy_probe()
591 		.name	= "mtk-xsphy",
599 MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");