112 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_prepare()  local
114 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);  in mtk_hdmi_pll_prepare()
115 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);  in mtk_hdmi_pll_prepare()
116 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);  in mtk_hdmi_pll_prepare()
117 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);  in mtk_hdmi_pll_prepare()
119 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);  in mtk_hdmi_pll_prepare()
121 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);  in mtk_hdmi_pll_prepare()
122 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);  in mtk_hdmi_pll_prepare()
129 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_unprepare()  local
131 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);  in mtk_hdmi_pll_unprepare()
132 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);  in mtk_hdmi_pll_unprepare()
134 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);  in mtk_hdmi_pll_unprepare()
136 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);  in mtk_hdmi_pll_unprepare()
137 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);  in mtk_hdmi_pll_unprepare()
138 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);  in mtk_hdmi_pll_unprepare()
145 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_round_rate()  local
147 	hdmi_phy->pll_rate = rate;  in mtk_hdmi_pll_round_rate()
159 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_set_rate()  local
166 	dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,  in mtk_hdmi_pll_set_rate()
180 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,  in mtk_hdmi_pll_set_rate()
182 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);  in mtk_hdmi_pll_set_rate()
183 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,  in mtk_hdmi_pll_set_rate()
186 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,  in mtk_hdmi_pll_set_rate()
188 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,  in mtk_hdmi_pll_set_rate()
191 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,  in mtk_hdmi_pll_set_rate()
193 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,  in mtk_hdmi_pll_set_rate()
199 		mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,  in mtk_hdmi_pll_set_rate()
203 		hdmi_ibias = hdmi_phy->ibias;  in mtk_hdmi_pll_set_rate()
205 		mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,  in mtk_hdmi_pll_set_rate()
209 		hdmi_ibias = hdmi_phy->ibias_up;  in mtk_hdmi_pll_set_rate()
211 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,  in mtk_hdmi_pll_set_rate()
220 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,  in mtk_hdmi_pll_set_rate()
223 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,  in mtk_hdmi_pll_set_rate()
224 			  (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |  in mtk_hdmi_pll_set_rate()
225 			  (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |  in mtk_hdmi_pll_set_rate()
226 			  (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |  in mtk_hdmi_pll_set_rate()
227 			  (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),  in mtk_hdmi_pll_set_rate()
230 	mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,  in mtk_hdmi_pll_set_rate()
245 	struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);  in mtk_hdmi_pll_recalc_rate()  local
247 	return hdmi_phy->pll_rate;  in mtk_hdmi_pll_recalc_rate()
258 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)  in mtk_hdmi_phy_enable_tmds()  argument
260 	mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,  in mtk_hdmi_phy_enable_tmds()
266 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)  in mtk_hdmi_phy_disable_tmds()  argument
268 	mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,  in mtk_hdmi_phy_disable_tmds()