Lines Matching full:selection

29  * [25] mipi dsi pll clock selection.
32  * [11] mipi divider clk selection.
51 /* [31] clk lane tx_hs_en control selection.
54  * [29] clk lane tx_lp_en contrl selection.
57  * [27] chan0 tx_hs_en control selection.
60  * [25] chan0 tx_lp_en control selection.
63  * [23] chan0 rx_lp_en control selection.
66  * [21] chan0 contention detection enable control selection.
69  * [19] chan1 tx_hs_en control selection.
72  * [17] chan1 tx_lp_en control selection.
75  * [15] chan2 tx_hs_en control selection.
78  * [13] chan2 tx_lp_en control selection.
81  * [11] chan3 tx_hs_en control selection.
84  * [9]  chan3 tx_lp_en control selection.