1 // SPDX-License-Identifier: GPL-2.0
3  * Meson AXG MIPI DPHY driver
29  * [25] mipi dsi pll clock selection.
31  * [12] mipi HSbyteclk enable.
32  * [11] mipi divider clk selection.
33  *		1: select the mipi DDRCLKHS from clock divider.
35  * [10] mipi clock divider control.
37  * [9]  mipi divider output enable.
38  * [8]  mipi divider counter enable.
47  * [0]  enalbe the MIPI DPHY TxDDRClk.
129 /* wait time to  MIPI DIS analog ready. */
187 	ret = phy_init(priv->analog);  in phy_meson_axg_mipi_dphy_init()
191 	ret = reset_control_reset(priv->reset);  in phy_meson_axg_mipi_dphy_init()
204 	ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);  in phy_meson_axg_mipi_dphy_configure()
208 	ret = phy_configure(priv->analog, opts);  in phy_meson_axg_mipi_dphy_configure()
212 	memcpy(&priv->config, opts, sizeof(priv->config));  in phy_meson_axg_mipi_dphy_configure()
223 	ret = phy_power_on(priv->analog);  in phy_meson_axg_mipi_dphy_power_on()
228 	regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,  0x1);  in phy_meson_axg_mipi_dphy_power_on()
229 	regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,  in phy_meson_axg_mipi_dphy_power_on()
235 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(9), BIT(9));  in phy_meson_axg_mipi_dphy_power_on()
238 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(12), BIT(12));  in phy_meson_axg_mipi_dphy_power_on()
239 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), BIT(31));  in phy_meson_axg_mipi_dphy_power_on()
240 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), 0);  in phy_meson_axg_mipi_dphy_power_on()
243 	temp = (1000000 * 100) / (priv->config.hs_clk_rate / 1000);  in phy_meson_axg_mipi_dphy_power_on()
246 	regmap_write(priv->regmap, MIPI_DSI_CLK_TIM,  in phy_meson_axg_mipi_dphy_power_on()
247 		     DIV_ROUND_UP(priv->config.clk_trail, temp) |  in phy_meson_axg_mipi_dphy_power_on()
248 		     (DIV_ROUND_UP(priv->config.clk_post +  in phy_meson_axg_mipi_dphy_power_on()
249 				   priv->config.hs_trail, temp) << 8) |  in phy_meson_axg_mipi_dphy_power_on()
250 		     (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |  in phy_meson_axg_mipi_dphy_power_on()
251 		     (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));  in phy_meson_axg_mipi_dphy_power_on()
252 	regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,  in phy_meson_axg_mipi_dphy_power_on()
253 		     DIV_ROUND_UP(priv->config.clk_pre, temp));  in phy_meson_axg_mipi_dphy_power_on()
255 	regmap_write(priv->regmap, MIPI_DSI_HS_TIM,  in phy_meson_axg_mipi_dphy_power_on()
256 		     DIV_ROUND_UP(priv->config.hs_exit, temp) |  in phy_meson_axg_mipi_dphy_power_on()
257 		     (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) |  in phy_meson_axg_mipi_dphy_power_on()
258 		     (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) |  in phy_meson_axg_mipi_dphy_power_on()
259 		     (DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24));  in phy_meson_axg_mipi_dphy_power_on()
261 	regmap_write(priv->regmap, MIPI_DSI_LP_TIM,  in phy_meson_axg_mipi_dphy_power_on()
262 		     DIV_ROUND_UP(priv->config.lpx, temp) |  in phy_meson_axg_mipi_dphy_power_on()
263 		     (DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) |  in phy_meson_axg_mipi_dphy_power_on()
264 		     (DIV_ROUND_UP(priv->config.ta_go, temp) << 16) |  in phy_meson_axg_mipi_dphy_power_on()
265 		     (DIV_ROUND_UP(priv->config.ta_get, temp) << 24));  in phy_meson_axg_mipi_dphy_power_on()
267 	regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100);  in phy_meson_axg_mipi_dphy_power_on()
268 	regmap_write(priv->regmap, MIPI_DSI_INIT_TIM,  in phy_meson_axg_mipi_dphy_power_on()
269 		     DIV_ROUND_UP(priv->config.init * NSEC_PER_MSEC, temp));  in phy_meson_axg_mipi_dphy_power_on()
270 	regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM,  in phy_meson_axg_mipi_dphy_power_on()
271 		     DIV_ROUND_UP(priv->config.wakeup * NSEC_PER_MSEC, temp));  in phy_meson_axg_mipi_dphy_power_on()
272 	regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C);  in phy_meson_axg_mipi_dphy_power_on()
273 	regmap_write(priv->regmap, MIPI_DSI_ULPS_CHECK, 0x927C);  in phy_meson_axg_mipi_dphy_power_on()
274 	regmap_write(priv->regmap, MIPI_DSI_LP_WCHDOG, 0x1000);  in phy_meson_axg_mipi_dphy_power_on()
275 	regmap_write(priv->regmap, MIPI_DSI_TURN_WCHDOG, 0x1000);  in phy_meson_axg_mipi_dphy_power_on()
278 	switch (priv->config.lanes) {  in phy_meson_axg_mipi_dphy_power_on()
280 		regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xe);  in phy_meson_axg_mipi_dphy_power_on()
283 		regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xc);  in phy_meson_axg_mipi_dphy_power_on()
286 		regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0x8);  in phy_meson_axg_mipi_dphy_power_on()
290 		regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0);  in phy_meson_axg_mipi_dphy_power_on()
295 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(1), BIT(1));  in phy_meson_axg_mipi_dphy_power_on()
304 	regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xf);  in phy_meson_axg_mipi_dphy_power_off()
305 	regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31));  in phy_meson_axg_mipi_dphy_power_off()
307 	phy_power_off(priv->analog);  in phy_meson_axg_mipi_dphy_power_off()
317 	ret = phy_exit(priv->analog);  in phy_meson_axg_mipi_dphy_exit()
321 	return reset_control_reset(priv->reset);  in phy_meson_axg_mipi_dphy_exit()
335 	struct device *dev = &pdev->dev;  in phy_meson_axg_mipi_dphy_probe()
345 		return -ENOMEM;  in phy_meson_axg_mipi_dphy_probe()
347 	priv->dev = dev;  in phy_meson_axg_mipi_dphy_probe()
355 	priv->regmap = devm_regmap_init_mmio(dev, base,  in phy_meson_axg_mipi_dphy_probe()
357 	if (IS_ERR(priv->regmap))  in phy_meson_axg_mipi_dphy_probe()
358 		return PTR_ERR(priv->regmap);  in phy_meson_axg_mipi_dphy_probe()
360 	priv->clk = devm_clk_get(dev, "pclk");  in phy_meson_axg_mipi_dphy_probe()
361 	if (IS_ERR(priv->clk))  in phy_meson_axg_mipi_dphy_probe()
362 		return PTR_ERR(priv->clk);  in phy_meson_axg_mipi_dphy_probe()
364 	priv->reset = devm_reset_control_get(dev, "phy");  in phy_meson_axg_mipi_dphy_probe()
365 	if (IS_ERR(priv->reset))  in phy_meson_axg_mipi_dphy_probe()
366 		return PTR_ERR(priv->reset);  in phy_meson_axg_mipi_dphy_probe()
368 	priv->analog = devm_phy_get(dev, "analog");  in phy_meson_axg_mipi_dphy_probe()
369 	if (IS_ERR(priv->analog))  in phy_meson_axg_mipi_dphy_probe()
370 		return PTR_ERR(priv->analog);  in phy_meson_axg_mipi_dphy_probe()
372 	ret = clk_prepare_enable(priv->clk);  in phy_meson_axg_mipi_dphy_probe()
376 	ret = reset_control_deassert(priv->reset);  in phy_meson_axg_mipi_dphy_probe()
383 		if (ret != -EPROBE_DEFER)  in phy_meson_axg_mipi_dphy_probe()
397 	{ .compatible = "amlogic,axg-mipi-dphy", },
405 		.name		= "phy-meson-axg-mipi-dphy",
412 MODULE_DESCRIPTION("Meson AXG MIPI DPHY driver");