44 	MRPC_IDLE = 0,
156 		memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE);  in mrpc_cmd_submit()
184 	return 0;  in mrpc_queue_cmd()
207 	stuser->return_code = 0;  in mrpc_complete_cmd()
216 	if (stuser->return_code != 0)  in mrpc_complete_cmd()
230 	stdev->mrpc_busy = 0;  in mrpc_complete_cmd()
305 	buf[len + 1] = 0;  in io_string_show()
307 	for (i = len - 1; i > 0; i--) {  in io_string_show()
311 		buf[i + 1] = 0;  in io_string_show()
432 	return 0;  in switchtec_dev_open()
441 	return 0;  in switchtec_dev_release()
454 	return 0;  in lock_mutex_and_test_alive()
539 		if (rc < 0)  in switchtec_dev_read()
584 	__poll_t ret = 0;  in switchtec_dev_poll()
606 	struct switchtec_ioctl_flash_info info = {0};  in ioctl_flash_info()
622 	return 0;  in ioctl_flash_info()
669 		set_fw_info_part(info, &fi->vendor[0]);  in flash_part_info_gen3()
699 	return 0;  in flash_part_info_gen3()
776 		set_fw_info_part(info, &fi->vendor[0]);  in flash_part_info_gen4()
803 	return 0;  in flash_part_info_gen4()
810 	struct switchtec_ioctl_flash_part_info info = {0};  in ioctl_flash_part_info()
830 	return 0;  in ioctl_flash_part_info()
841 	int ret = 0;  in ioctl_event_summary()
851 	for (i = 0; i < stdev->partition_count; i++) {  in ioctl_event_summary()
856 	for (i = 0; i < stdev->pff_csr_count; i++) {  in ioctl_event_summary()
942 	if (event_id < 0 || event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)  in event_hdr_addr()
950 		else if (index < 0 || index >= stdev->partition_count)  in event_hdr_addr()
953 		if (index < 0 || index >= stdev->pff_csr_count)  in event_hdr_addr()
972 	for (i = 0; i < ARRAY_SIZE(ctl->data); i++)  in event_ctl()
976 	ctl->count = (hdr >> 5) & 0xFF;  in event_ctl()
1000 	ctl->flags = 0;  in event_ctl()
1010 	return 0;  in event_ctl()
1041 		for (ctl.index = 0; ctl.index < nr_idxs; ctl.index++) {  in ioctl_event_ctl()
1044 			if (ret < 0)  in ioctl_event_ctl()
1049 		if (ret < 0)  in ioctl_event_ctl()
1056 	return 0;  in ioctl_event_ctl()
1071 	for (part = 0; part < stdev->partition_count; part++) {  in ioctl_pff_to_port()
1077 			p.port = 0;  in ioctl_pff_to_port()
1087 		for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {  in ioctl_pff_to_port()
1103 	return 0;  in ioctl_pff_to_port()
1123 	case 0:  in ioctl_port_to_pff()
1141 	return 0;  in ioctl_port_to_pff()
1215 	int occurred = 0;  in check_link_state_events()
1217 	for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in check_link_state_events()
1220 		count = (reg >> 5) & 0xFF;  in check_link_state_events()
1236 	for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in enable_link_state_events()
1255 		iowrite32(0, &stdev->mmio_mrpc->dma_en);  in stdev_release()
1257 		writeq(0, &stdev->mmio_mrpc->dma_addr);  in stdev_release()
1307 	stdev->mrpc_busy = 0;  in stdev_create()
1312 	atomic_set(&stdev->event_cnt, 0);  in stdev_create()
1321 	minor = ida_simple_get(&switchtec_minor_ida, 0, 0,  in stdev_create()
1323 	if (minor < 0) {  in stdev_create()
1352 		return 0;  in mask_event()
1364 	int count = 0;  in mask_all_events()
1367 		for (idx = 0; idx < stdev->partition_count; idx++)  in mask_all_events()
1370 		for (idx = 0; idx < stdev->pff_csr_count; idx++) {  in mask_all_events()
1377 		count += mask_event(stdev, eid, 0);  in mask_all_events()
1388 	int eid, event_count = 0;  in switchtec_event_isr()
1400 	for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) {  in switchtec_event_isr()
1447 	if (nvecs < 0)  in switchtec_init_isr()
1451 	if (event_irq < 0 || event_irq >= nvecs)  in switchtec_init_isr()
1455 	if (event_irq < 0)  in switchtec_init_isr()
1459 				switchtec_event_isr, 0,  in switchtec_init_isr()
1469 	if (dma_mrpc_irq < 0 || dma_mrpc_irq >= nvecs)  in switchtec_init_isr()
1473 	if (dma_mrpc_irq < 0)  in switchtec_init_isr()
1477 				switchtec_dma_mrpc_isr, 0,  in switchtec_init_isr()
1489 	for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {  in init_pff()
1505 	for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {  in init_pff()
1530 	res_start = pci_resource_start(pdev, 0);  in switchtec_init_pci()
1531 	res_len = pci_resource_len(pdev, 0);  in switchtec_init_pci()
1575 		return 0;  in switchtec_init_pci()
1577 	if (ioread32(&stdev->mmio_mrpc->dma_ver) == 0)  in switchtec_init_pci()
1578 		return 0;  in switchtec_init_pci()
1587 	return 0;  in switchtec_init_pci()
1629 	return 0;  in switchtec_pci_probe()
1659 		.class_mask = 0xFFFFFFFF, \
1668 		.class_mask = 0xFFFFFFFF, \
1673 	SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3),  //PFX 24xG3
1674 	SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3),  //PFX 32xG3
1675 	SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3),  //PFX 48xG3
1676 	SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3),  //PFX 64xG3
1677 	SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3),  //PFX 80xG3
1678 	SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3),  //PFX 96xG3
1679 	SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3),  //PSX 24xG3
1680 	SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3),  //PSX 32xG3
1681 	SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3),  //PSX 48xG3
1682 	SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3),  //PSX 64xG3
1683 	SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3),  //PSX 80xG3
1684 	SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3),  //PSX 96xG3
1685 	SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3),  //PAX 24XG3
1686 	SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3),  //PAX 32XG3
1687 	SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3),  //PAX 48XG3
1688 	SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3),  //PAX 64XG3
1689 	SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3),  //PAX 80XG3
1690 	SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3),  //PAX 96XG3
1691 	SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3),  //PFXL 24XG3
1692 	SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3),  //PFXL 32XG3
1693 	SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3),  //PFXL 48XG3
1694 	SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3),  //PFXL 64XG3
1695 	SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3),  //PFXL 80XG3
1696 	SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3),  //PFXL 96XG3
1697 	SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3),  //PFXI 24XG3
1698 	SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3),  //PFXI 32XG3
1699 	SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3),  //PFXI 48XG3
1700 	SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3),  //PFXI 64XG3
1701 	SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3),  //PFXI 80XG3
1702 	SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3),  //PFXI 96XG3
1703 	SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4),  //PFX 100XG4
1704 	SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4),  //PFX 84XG4
1705 	SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4),  //PFX 68XG4
1706 	SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4),  //PFX 52XG4
1707 	SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4),  //PFX 36XG4
1708 	SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4),  //PFX 28XG4
1709 	SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4),  //PSX 100XG4
1710 	SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4),  //PSX 84XG4
1711 	SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4),  //PSX 68XG4
1712 	SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4),  //PSX 52XG4
1713 	SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4),  //PSX 36XG4
1714 	SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4),  //PSX 28XG4
1715 	SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4),  //PAX 100XG4
1716 	SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4),  //PAX 84XG4
1717 	SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4),  //PAX 68XG4
1718 	SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4),  //PAX 52XG4
1719 	SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4),  //PAX 36XG4
1720 	SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4),  //PAX 28XG4
1721 	{0}
1736 	rc = alloc_chrdev_region(&switchtec_devt, 0, max_devices,  in switchtec_init()
1753 	return 0;  in switchtec_init()