Lines Matching +full:pci +full:- +full:host +full:- +full:cam +full:- +full:generic
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
11 * Init/reset quirks for USB host controllers should be in the USB quirks
18 #include <linux/pci.h>
33 #include "pci.h"
63 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
64 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
65 (f->vendor == dev->vendor || in pci_do_fixups()
66 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
67 (f->device == dev->device || in pci_do_fixups()
68 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
71 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
73 hook = f->hook; in pci_do_fixups()
162 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); in pci_apply_final_quirks()
169 * value shared by all PCI devices. If there's a in pci_apply_final_quirks()
187 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, in pci_apply_final_quirks()
197 * Decoding should be disabled for a PCI device during BAR sizing to avoid
198 * conflict. But doing so may cause problems on host bridge and perhaps other
199 * key system devices. For devices that need to have mmio decoding always-on,
200 * we need to set the dev->mmio_always_on bit.
204 dev->mmio_always_on = 1; in quirk_mmio_always_on()
244 * contacts at VIA ask them for me please -- Alan
288 /* Chipsets where PCI->PCI transfers vanish or hang */
292 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); in quirk_nopcipci()
305 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); in quirk_nopciamd()
315 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_triton()
325 * VIA Apollo KT133 needs PCI latency patch
326 * Made according to a Windows driver-based patch by George E. Breese;
327 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
328 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
347 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
351 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
359 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
364 * Ok we have the problem. Now set the PCI master grant to occur in quirk_vialatency()
365 * every master grant. The apparent bug is that under high PCI load in quirk_vialatency()
379 * "Master priority rotation on every PCI master grant" in quirk_vialatency()
400 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_viaetbf()
409 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_vsfx()
423 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_alimagik()
434 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_natoma()
446 * This chip can cause PCI parity errors if config register 0xA0 is read
451 dev->cfg_size = 0xA0; in quirk_citrine()
461 dev->cfg_size = 0x600; in quirk_nfp6000()
474 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
476 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
477 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
478 r->start = 0; in quirk_extend_bar_to_page()
479 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
489 * If it's needed, re-allocate the region.
493 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
495 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
496 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
497 r->start = 0; in quirk_s3_64M()
498 r->end = 0x3ffffff; in quirk_s3_64M()
509 struct resource *res = dev->resource + pos; in quirk_io()
516 res->name = pci_name(dev); in quirk_io()
517 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
518 res->flags |= in quirk_io()
520 region &= ~(size - 1); in quirk_io()
522 /* Convert from PCI bus to resource space */ in quirk_io()
524 bus_region.end = region + size - 1; in quirk_io()
525 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
533 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
537 * CS553x's ISA PCI BARs may also be read-only (ref:
538 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
559 struct resource *res = dev->resource + nr; in quirk_io_region()
562 region &= ~(size - 1); in quirk_io_region()
567 res->name = pci_name(dev); in quirk_io_region()
568 res->flags = IORESOURCE_IO; in quirk_io_region()
570 /* Convert from PCI bus to resource space */ in quirk_io_region()
572 bus_region.end = region + size - 1; in quirk_io_region()
573 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
581 * between 0x3b0->0x3bb or read 0x3d3
599 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
600 * defines as "USB device (not host controller)". The dwc3 driver can then
605 u32 class = pdev->class; in quirk_amd_nl_class()
607 /* Use "USB Device (not host controller)" class */ in quirk_amd_nl_class()
608 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_nl_class()
609 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_amd_nl_class()
610 class, pdev->class); in quirk_amd_nl_class()
616 * Synopsys USB 3.x host HAPS platform has a class code of
618 * devices should use dwc3-haps driver. Change these devices' class code to
619 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
624 u32 class = pdev->class; in quirk_synopsys_haps()
626 switch (pdev->device) { in quirk_synopsys_haps()
630 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
631 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
632 class, pdev->class); in quirk_synopsys_haps()
679 base &= -size; in piix4_io_quirk()
680 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
705 base &= -size; in piix4_mem_quirk()
706 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
758 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
832 base &= ~(size-1); in ich6_lpc_generic_decode()
838 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
846 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
847 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
848 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
865 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
877 /* ICH7-10 has the same common LPC generic IO decode registers */
883 /* And have 4 ICH7+ generic decodes */ in quirk_ich7_lpc()
884 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
885 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
886 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
887 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
909 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
926 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
945 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
946 * back-to-back: Disable fast back-to-back on the secondary bus segment
953 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
954 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
968 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
971 * TODO: When we have device-specific interrupt routers, this code will go
981 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
993 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1005 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1013 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1023 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1035 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1036 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1037 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1044 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1048 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1049 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1050 dev->revision); in quirk_amd_8131_mmrbc()
1051 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1061 * -jgarzik
1067 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ in quirk_via_acpi()
1071 d->irq = irq; in quirk_via_acpi()
1077 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1082 switch (dev->device) { in quirk_via_bridge()
1085 * The VT82C686 is special; it attaches to PCI and can have in quirk_via_bridge()
1089 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1090 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1117 * quirk_via_vlink - VIA VLink IRQ number update
1118 * @dev: PCI device
1121 * the IRQ line register which usually is not relevant for PCI cards, is
1132 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1135 new_irq = dev->irq; in quirk_via_vlink()
1142 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1143 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1168 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1188 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1200 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); in quirk_amd_ordering()
1211 * DreamWorks-provided workaround for Dunord I-3000 problem
1219 struct resource *r = &dev->resource[1]; in quirk_dunord()
1221 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1222 r->start = 0; in quirk_dunord()
1223 r->end = 0xffffff; in quirk_dunord()
1228 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1230 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1234 dev->transparent = 1; in quirk_transparent_bridge()
1240 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1241 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1269 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1275 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); in quirk_disable_pxb()
1283 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1294 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1314 pdev->class &= ~5; in quirk_svwks_csb5ide()
1316 /* PCI layer will sort out resources */ in quirk_svwks_csb5ide()
1321 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1331 pdev->class &= ~5; in quirk_ide_samemode()
1340 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1356 * This was originally an Alpha-specific thing, but it really fits here.
1357 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1361 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1366 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1368 * users to be irritated by just another PCI Device in the Win98 device
1372 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1374 * becomes necessary to do this tweak in two steps -- the chosen trigger
1375 * is either the Host bridge (preferred) or on-board VGA controller.
1388 * the DSDT and double-check that there is no code accessing the SMBus.
1394 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1395 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1396 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1397 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1403 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1404 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1405 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1407 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1410 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1411 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1415 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1416 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1420 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1421 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1422 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1425 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1426 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1432 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1433 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1438 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1439 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1440 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1443 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1444 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1449 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1450 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1451 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1456 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1457 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1463 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1464 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1468 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1469 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1470 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1474 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1475 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1476 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1480 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1481 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1482 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1483 /* Motherboard doesn't have Host bridge in asus_hides_smbus_hostbridge()
1485 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1488 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1489 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1493 /* Motherboard doesn't have Host bridge in asus_hides_smbus_hostbridge()
1494 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1500 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1501 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1503 /* Motherboard doesn't have host bridge in asus_hides_smbus_hostbridge()
1505 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1657 dev->device = devid; in quirk_sis_503()
1665 * and MC97 modem controller are disabled when a second PCI soundcard is
1667 * -- bjd
1674 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1675 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1700 * early on to make the additional device appear during the PCI scanning.
1708 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1714 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1717 switch (pdev->device) { in quirk_jmicron_ata()
1749 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1750 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1753 pdev->class = class >> 8; in quirk_jmicron_ata()
1778 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1779 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1780 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1793 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1797 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1802 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1809 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1816 pdev->no_msi = 1; in quirk_pcie_mch()
1825 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
1826 * actually on the AMBA bus. These fake PCI devices can support SVA via
1827 * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1829 * Normally stalling must not be enabled for PCI devices, since it would
1830 * break the PCI requirement for free-flowing writes and may lead to
1831 * deadlock. We expect PCI devices to support ATS and PRI if they want to
1832 * be fault-tolerant, so there's no ACPI binding to describe anything else,
1833 * even when a "PCI" device turns out to be a regular old SoC device
1839 PROPERTY_ENTRY_BOOL("dma-can-stall"), in quirk_huawei_pcie_sva()
1843 if (pdev->revision != 0x21 && pdev->revision != 0x30) in quirk_huawei_pcie_sva()
1846 pdev->pasid_no_tlp = 1; in quirk_huawei_pcie_sva()
1849 * Set the dma-can-stall property on ACPI platforms. Device tree in quirk_huawei_pcie_sva()
1852 if (!pdev->dev.of_node && in quirk_huawei_pcie_sva()
1853 device_add_properties(&pdev->dev, properties)) in quirk_huawei_pcie_sva()
1865 * together on certain PXH-based systems.
1869 dev->no_msi = 1; in quirk_pcie_pxh()
1879 * Some Intel PCI Express chipsets have trouble with downstream device
1885 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
1911 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
1914 dev->d3hot_delay = delay; in quirk_d3hot_delay()
1915 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
1916 dev->d3hot_delay); in quirk_d3hot_delay()
1921 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
1922 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
1932 * to be ineffective on the platforms in question; the PCI device appears to
1933 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1948 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
1959 .ident = "ASUSTek Computer INC. M2N-LR",
1962 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1971 * that a PCI device's interrupt handler is installed on the boot interrupt
1980 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
1982 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
2007 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2008 * 300641-004US, section 5.7.3.
2010 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2011 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2012 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2013 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2014 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2015 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2016 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2017 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2034 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2045 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2057 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2060 * Device 29 Func 5 Device IDs of IO-APIC
2096 /* Disable boot interrupts on HT-1000 */
2122 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2131 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2145 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2146 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2154 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2173 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2178 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2185 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2187 * Re-allocate the region if needed...
2191 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2193 if (r->start & 0x8) { in quirk_tc86c001_ide()
2194 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2195 r->start = 0; in quirk_tc86c001_ide()
2196 r->end = 0xf; in quirk_tc86c001_ide()
2204 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2208 * Re-allocate the regions to a 256-byte boundary if necessary.
2214 /* Fixed in revision 2 (PCI 9052). */ in quirk_plx_pci9050()
2215 if (dev->revision >= 2) in quirk_plx_pci9050()
2220 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2221 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2223 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2224 r->start = 0; in quirk_plx_pci9050()
2225 r->end = 0xff; in quirk_plx_pci9050()
2232 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2244 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2245 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2257 switch (dev->device) { in quirk_netmos()
2260 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2261 dev->subsystem_device == 0x0299) in quirk_netmos()
2270 dev->device, num_parallel, num_serial); in quirk_netmos()
2271 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2272 (dev->class & 0xff); in quirk_netmos()
2285 switch (dev->device) { in quirk_e100_interrupt()
2286 /* PCI IDs taken from drivers/net/e100.c */ in quirk_e100_interrupt()
2310 * re-enable them when it's ready. in quirk_e100_interrupt()
2321 if (dev->pm_cap) { in quirk_e100_interrupt()
2322 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2327 /* Convert from PCI bus to resource space. */ in quirk_e100_interrupt()
2376 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2383 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2392 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2401 u32 class = dev->class; in fixup_rev1_53c810()
2410 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2411 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2412 class, dev->class); in fixup_rev1_53c810()
2425 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2454 * Disable PCI Bus Parking and PCI Master read caching on CX700 in quirk_via_cx700_pci_parking_caching()
2455 * which causes unspecified timing errors with a VT6212L on the PCI in quirk_via_cx700_pci_parking_caching()
2458 * This quirk is only enabled if a second (on the external PCI bus) in quirk_via_cx700_pci_parking_caching()
2459 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2460 * host controller with the same PCI ID as the VT6212L. in quirk_via_cx700_pci_parking_caching()
2469 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2479 /* Turn off PCI Bus Parking */ in quirk_via_cx700_pci_parking_caching()
2482 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); in quirk_via_cx700_pci_parking_caching()
2488 /* Turn off PCI Master read caching */ in quirk_via_cx700_pci_parking_caching()
2491 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2497 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); in quirk_via_cx700_pci_parking_caching()
2523 * DRBs - this is where we expose device 6.
2524 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2566 if (dev->subordinate) { in quirk_disable_msi()
2568 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2578 * we use the possible vendor/device IDs of the host bridge for the
2585 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2587 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2604 while (pos && ttl--) { in msi_ht_cap_enabled()
2642 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2658 while (pos && ttl--) { in ht_enable_msi_mapping()
2679 * The P5N32-SLI motherboards from Asus have a problem with MSI
2688 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2689 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2690 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2691 dev->no_msi = 1; in nvenet_msi_disable()
2699 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2704 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2709 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2790 while (pos && ttl--) { in ht_check_msi_mapping()
2818 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2820 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2824 /* found next host bridge? */ in host_bridge_with_leaf()
2876 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
2877 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
2878 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
2913 while (pos && ttl--) { in ht_disable_msi_mapping()
2946 * a non-Hypertransport host bridge. Locate the host bridge... in __nv_msi_ht_cap_quirk()
2948 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
2951 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); in __nv_msi_ht_cap_quirk()
2957 /* Host bridge is to HT */ in __nv_msi_ht_cap_quirk()
2972 /* Host bridge is not to HT, disable HT MSI mapping on this device */ in __nv_msi_ht_cap_quirk()
2995 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
3004 * we need check PCI REVISION ID of SMBus controller to get SB700 in quirk_msi_intx_disable_ati_bug()
3012 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3013 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3020 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3022 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3086 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3090 * tested), since currently there is no standard way to disable only MSI-X.
3097 dev->no_msi = 1; in quirk_al_msi_disable()
3098 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3105 * Allow manual resource allocation for PCI hotplug bridges via
3106 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3108 * allocate resources when hotplug device is inserted and PCI bus is
3113 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3128 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3130 * MMC controller - so the SDHCI driver never sees them.
3134 * case that the relevant PCI registers to deactivate the MMC controller
3135 * live on PCI function 0, which might be the CardBus controller or the
3139 * other PCI functions shift up one level, e.g. function #2 becomes function
3140 * #1, and this will confuse the PCI core.
3154 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3185 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3192 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3194 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3195 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3196 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3197 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3199 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3200 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3237 * This is a quirk for masking VT-d spec-defined errors to platform error
3240 * on the RAS config settings of the platform) when a VT-d fault happens.
3243 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3259 u32 class = dev->class; in fixup_ti816x_class()
3262 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3263 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3264 class, dev->class); in fixup_ti816x_class()
3275 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3290 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3326 /* Intel 5000 series memory controllers and ports 2-7 */
3341 /* Intel 5100 series memory controllers and ports 2-7 */
3368 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3374 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3383 * and the interrupt ends up -somewhere-.
3396 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); in disable_igfx_irq()
3418 * PCI devices which are on Intel chips can skip the 10ms delay
3423 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3429 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3459 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3463 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3469 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3470 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3472 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3479 * DisINTx can be set but the interrupt status bit is non-functional.
3519 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3535 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3536 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3542 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3545 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3548 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3549 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3552 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3560 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3572 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3573 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3575 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3588 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3597 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3605 * The device will throw a Link Down error on AER-capable systems and
3639 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3640 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3644 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3645 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3661 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3662 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3663 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3664 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3682 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3686 * bridges leading to the NHI and to the tunnel PCI bridges.
3711 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3718 * device ID as those on the host, but they will not have the in quirk_apple_poweroff_thunderbolt()
3742 * Following are device-specific reset methods which can be used to
3743 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3749 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3779 return -ENOMEM; in reset_ivb_igd()
3810 /* Device-specific reset method for Chelsio T4-based adapters */
3817 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3818 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3820 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3821 return -ENOTTY; in reset_chelsio_generic_dev()
3847 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
3848 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
3849 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
3851 * MSI-X state. in reset_chelsio_generic_dev()
3853 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
3855 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
3864 * the original PCI Configuration Space Command word, and return in reset_chelsio_generic_dev()
3878 * FLR where config space reads from the device return -1. We seem to be
3880 * FLR. This quirk is generic for any NVMe class device requiring similar
3885 * Chapter 2: Required and optional PCI config registers
3895 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
3897 return -ENOTTY; in nvme_disable_and_flr()
3904 return -ENOTTY; in nvme_disable_and_flr()
3982 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3994 return -ENOTTY; in reset_hinic_vf_dev()
4000 return -ENOTTY; in reset_hinic_vf_dev()
4056 * These device-specific reset methods are here rather than in a driver
4057 * because when a host assigns a device to a guest VM, the host may need
4064 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
4065 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4066 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
4067 (i->device == dev->device || in pci_dev_specific_reset()
4068 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
4069 return i->reset(dev, probe); in pci_dev_specific_reset()
4072 return -ENOTTY; in pci_dev_specific_reset()
4077 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4078 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4091 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4092 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4145 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4155 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4159 * controller supports private devices, which can be hidden from PCI config
4180 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4185 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4190 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4191 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4195 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4196 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4197 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4198 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4199 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4216 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4229 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4234 * host memory. These aliases mark the whole VCA device as one IOMMU
4238 * what slot is used on other side. This quirk is intended for both host
4264 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4272 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4277 u32 class = pdev->class; in quirk_tw686x_class()
4280 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4281 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4282 class, pdev->class); in quirk_tw686x_class()
4300 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4371 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4387 * If a non-compliant device generates a completion with a different
4389 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4393 * If the non-compliant device generates completions with zero attributes
4415 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4430 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely in quirk_chelsio_T5_disable_root_port_attributes()
4433 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4440 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4458 * AMD has indicated that the devices below do not support peer-to-peer
4461 * peer-to-peer between functions can claim to support a subset of ACS.
4473 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4474 * 1002:4384 SBx00 PCI to PCI Bridge
4479 * 1022:780f [AMD] FCH PCI Bridge
4489 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4490 return -ENODEV; in pci_quirk_amd_sb_acs()
4495 return -ENODEV; in pci_quirk_amd_sb_acs()
4504 return -ENODEV; in pci_quirk_amd_sb_acs()
4513 switch (dev->device) { in pci_quirk_cavium_acs_match()
4530 return -ENOTTY; in pci_quirk_cavium_acs()
4547 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4557 * But the implementation could block peer-to-peer transactions between them
4558 * and provide ACS-like functionality.
4565 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4567 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4579 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4594 /* Lynxpoint-H PCH */
4597 /* Lynxpoint-LP PCH */
4616 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4621 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4630 return -ENOTTY; in pci_quirk_intel_pch_acs()
4632 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4640 * These QCOM Root Ports do provide ACS-like features to disable peer
4644 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4670 return -ENOTTY; in pci_quirk_al_acs()
4674 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4675 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4692 * dword accesses to them. This applies to the following PCI Device IDs, as
4695 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4696 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4704 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4705 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4708 * 0xa290-0xa29f PCI Express Root port #{0-16}
4709 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4715 * August 2017, Revision 002, Document#: 334660-002)[6]
4718 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4720 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4722 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4723 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4724 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4725 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4726 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4727 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4728 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4735 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4753 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4755 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4757 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4774 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4776 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4788 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4789 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4792 return -ENOTTY; in pci_quirk_rciep_acs()
4802 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4872 /* 82571 (Quads omitted due to non-ACS switch) */
4889 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4890 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4893 /* Cavium multi-function devices */
4897 /* APM X-Gene */
4908 /* Broadcom multi-function device */
4913 /* Zhaoxin multi-function devices */
4918 /* LX2xx0A : without security features + CAN-FD */
4922 /* LX2xx0C : security features + CAN-FD */
4934 /* LX2xx2A : without security features + CAN-FD */
4938 /* LX2xx2C : security features + CAN-FD */
4956 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4957 * @dev: PCI device
4961 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4973 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
4974 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
4977 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
4978 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
4979 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
4980 (i->device == dev->device || in pci_dev_specific_acs_enabled()
4981 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
4982 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
4988 return -ENOTTY; in pci_dev_specific_acs_enabled()
5000 /* Backbone Peer Non-Posted Disable */
5020 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5023 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
5028 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
5032 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
5063 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which in pci_quirk_enable_intel_rp_mpc_acs()
5080 * if dev->external_facing || dev->untrusted
5085 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
5094 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5107 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5109 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5111 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5121 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5137 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5139 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5141 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5177 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5178 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5179 (p->device == dev->device || in pci_dev_specific_enable_acs()
5180 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5181 p->enable_acs) { in pci_dev_specific_enable_acs()
5182 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5188 return -ENOTTY; in pci_dev_specific_enable_acs()
5198 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5199 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5200 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5201 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5202 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5203 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5209 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5213 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5227 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5247 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5260 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5262 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5264 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5266 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5269 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5279 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5280 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5281 state->cap.size = size; in quirk_intel_qat_vf_cap()
5282 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5290 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5299 * AMD Starship USB 3.0 Host Controller 0x148c
5300 * AMD Matisse USB 3.0 Host Controller 0x149c
5307 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5317 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5322 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5325 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5343 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || in quirk_amd_harvest_no_ats()
5344 (pdev->device == 0x7340 && pdev->revision != 0xc5) || in quirk_amd_harvest_no_ats()
5345 (pdev->device == 0x7341 && pdev->revision != 0x00)) in quirk_amd_harvest_no_ats()
5348 if (pdev->device == 0x15d8) { in quirk_amd_harvest_no_ats()
5349 if (pdev->revision == 0xcf && in quirk_amd_harvest_no_ats()
5350 pdev->subsystem_vendor == 0xea50 && in quirk_amd_harvest_no_ats()
5351 (pdev->subsystem_device == 0xce19 || in quirk_amd_harvest_no_ats()
5352 pdev->subsystem_device == 0xcc10 || in quirk_amd_harvest_no_ats()
5353 pdev->subsystem_device == 0xcc08)) in quirk_amd_harvest_no_ats()
5361 pdev->ats_cap = 0; in quirk_amd_harvest_no_ats()
5381 pdev->no_msi = 1; in quirk_fsl_no_msi()
5386 * Although not allowed by the spec, some multi-function devices have
5399 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5402 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5403 pdev->bus->number, in pci_create_device_link()
5404 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5405 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5410 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5418 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5438 * Create device link for GPUs with integrated USB xHCI Host
5451 * Create device link for GPUs with integrated Type-C UCSI controller
5452 * to VGA. Currently there is no class code defined for UCSI device over PCI
5454 * over PCI gets a class code.
5478 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5489 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5491 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5502 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5504 * Item #36 - Downstream port applies ACS Source Validation to Completions
5505 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5517 * write, so we do config reads until we receive a non-Config Request Retry
5528 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5530 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5542 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5546 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5556 * originating requestor ID TLPs which access host memory on peer NTB
5586 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5588 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5589 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5604 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5621 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
5722 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5723 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5766 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
5778 * 7.3.27, 7.3.29-7.3.31.
5784 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
5787 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
5794 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()