145 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in enable_ecrc_checking()
169 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in disable_ecrc_checking()
258 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_nonfatal_status()
259 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_nonfatal_status()
277 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_fatal_status()
278 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_fatal_status()
305 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);  in pci_aer_raw_clear_status()
309 	pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in pci_aer_raw_clear_status()
312 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_raw_clear_status()
340 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);  in pci_save_aer_state()
341 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);  in pci_save_aer_state()
342 	pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);  in pci_save_aer_state()
343 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);  in pci_save_aer_state()
345 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);  in pci_save_aer_state()
866 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in is_error_source()
867 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);  in is_error_source()
869 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in is_error_source()
870 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);  in is_error_source()
1057 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,  in aer_get_device_error_info()
1059 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,  in aer_get_device_error_info()
1069 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,  in aer_get_device_error_info()
1071 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,  in aer_get_device_error_info()
1077 		pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);  in aer_get_device_error_info()
1082 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1084 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1086 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1088 			pci_read_config_dword(dev,  in aer_get_device_error_info()
1198 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);  in aer_irq()
1202 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);  in aer_irq()
1272 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_enable_rootport()
1274 	pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, &reg32);  in aer_enable_rootport()
1276 	pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, &reg32);  in aer_enable_rootport()
1286 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_enable_rootport()
1310 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_disable_rootport()
1315 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_disable_rootport()
1404 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1423 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_root_reset()
1427 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()