Lines Matching +full:retain +full:- +full:state +full:- +full:suspended
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
67 unsigned int delay = dev->d3hot_delay; in pci_dev_d3_sleep()
78 return dev->reset_methods[0] != 0; in pci_reset_supported()
97 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
108 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
125 * measured in 32-bit words, not bytes.
170 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
181 max = bus->busn_res.end; in pci_bus_max_busnr()
182 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
192 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
204 return -EIO; in pci_status_get_and_clear_errors()
218 struct resource *res = &pdev->resource[bar]; in __pci_ioremap_resource()
219 resource_size_t start = res->start; in __pci_ioremap_resource()
225 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in __pci_ioremap_resource()
250 * pci_dev_str_match_path - test if a path string matches a device
261 * A path for a device can be obtained using 'lspci -t'. Using a path
278 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
280 return -ENOMEM; in pci_dev_str_match_path()
288 ret = -EINVAL; in pci_dev_str_match_path()
292 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
318 ret = -EINVAL; in pci_dev_str_match_path()
323 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
324 bus == dev->bus->number && in pci_dev_str_match_path()
325 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
333 * pci_dev_str_match - test if a string matches a device
350 * through the use of 'lspci -t'.
355 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
377 return -EINVAL; in pci_dev_str_match()
385 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
386 (!device || device == dev->device) && in pci_dev_str_match()
388 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
390 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
420 while ((*ttl)--) { in __pci_find_next_cap_ttl()
446 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
472 * pci_find_capability - query for devices' capabilities
487 * %PCI_CAP_ID_PCIX PCI-X
494 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
496 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
503 * pci_bus_find_capability - query for devices' capabilities
530 * pci_find_next_ext_capability - Find an extended capability
538 * vendor-specific capability, and this provides a way to find them all.
547 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
549 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
565 while (ttl-- > 0) { in pci_find_next_ext_capability()
582 * pci_find_ext_capability - Find an extended capability
602 * pci_get_dsn - Read and return the 8-byte Device Serial Number
645 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
655 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
664 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
683 * pci_find_ht_capability - query a device's HyperTransport capabilities
697 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
706 * pci_find_vsec_capability - Find a vendor-specific extended capability
709 * @cap: Vendor-specific capability ID
720 if (vendor != dev->vendor) in pci_find_vsec_capability()
736 * pci_find_parent_resource - return resource region of parent bus of given
747 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
760 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
761 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
766 * be both a positively-decoded aperture and a in pci_find_parent_resource()
767 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
768 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
780 * pci_find_resource - Return matching PCI device resource
793 struct resource *r = &dev->resource[i]; in pci_find_resource()
795 if (r->start && resource_contains(r, res)) in pci_find_resource()
804 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
819 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
832 * pci_request_acs - ask for ACS to be enabled if supported
842 * pci_disable_acs_redir - disable ACS redirect capabilities
883 pos = dev->acs_cap; in pci_disable_acs_redir()
900 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
909 pos = dev->acs_cap; in pci_std_enable_acs()
929 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_std_enable_acs()
936 * pci_enable_acs - enable ACS if hardware support it
961 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
979 if (!ops->is_manageable || !ops->set_state || !ops->get_state || in pci_set_platform_pm()
980 !ops->choose_state || !ops->set_wakeup || !ops->need_resume) in pci_set_platform_pm()
981 return -EINVAL; in pci_set_platform_pm()
988 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; in platform_pci_power_manageable()
994 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; in platform_pci_set_power_state()
999 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN; in platform_pci_get_power_state()
1004 if (pci_platform_pm && pci_platform_pm->refresh_state) in platform_pci_refresh_power_state()
1005 pci_platform_pm->refresh_state(dev); in platform_pci_refresh_power_state()
1011 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; in platform_pci_choose_state()
1017 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV; in platform_pci_set_wakeup()
1022 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false; in platform_pci_need_resume()
1027 if (pci_platform_pm && pci_platform_pm->bridge_d3) in platform_pci_bridge_d3()
1028 return pci_platform_pm->bridge_d3(dev); in platform_pci_bridge_d3()
1033 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1036 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1039 * -EINVAL if the requested state is invalid.
1040 * -EIO if device does not support PCI PM or its PM capabilities register has a
1041 * wrong version, or device doesn't support the requested state.
1042 * 0 if device already is in the requested state.
1043 * 0 if device's power state has been successfully changed.
1045 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) in pci_raw_set_power_state() argument
1051 if (dev->current_state == state) in pci_raw_set_power_state()
1054 if (!dev->pm_cap) in pci_raw_set_power_state()
1055 return -EIO; in pci_raw_set_power_state()
1057 if (state < PCI_D0 || state > PCI_D3hot) in pci_raw_set_power_state()
1058 return -EINVAL; in pci_raw_set_power_state()
1061 * Validate transition: We can enter D0 from any state, but if in pci_raw_set_power_state()
1062 * we're already in a low-power state, we can only go deeper. E.g., in pci_raw_set_power_state()
1066 if (state != PCI_D0 && dev->current_state <= PCI_D3cold in pci_raw_set_power_state()
1067 && dev->current_state > state) { in pci_raw_set_power_state()
1069 pci_power_name(dev->current_state), in pci_raw_set_power_state()
1070 pci_power_name(state)); in pci_raw_set_power_state()
1071 return -EINVAL; in pci_raw_set_power_state()
1074 /* Check if this device supports the desired state */ in pci_raw_set_power_state()
1075 if ((state == PCI_D1 && !dev->d1_support) in pci_raw_set_power_state()
1076 || (state == PCI_D2 && !dev->d2_support)) in pci_raw_set_power_state()
1077 return -EIO; in pci_raw_set_power_state()
1079 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_raw_set_power_state()
1081 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n", in pci_raw_set_power_state()
1082 pci_power_name(dev->current_state), in pci_raw_set_power_state()
1083 pci_power_name(state)); in pci_raw_set_power_state()
1084 return -EIO; in pci_raw_set_power_state()
1092 switch (dev->current_state) { in pci_raw_set_power_state()
1097 pmcsr |= state; in pci_raw_set_power_state()
1101 case PCI_UNKNOWN: /* Boot-up */ in pci_raw_set_power_state()
1111 /* Enter specified state */ in pci_raw_set_power_state()
1112 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_raw_set_power_state()
1118 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) in pci_raw_set_power_state()
1120 else if (state == PCI_D2 || dev->current_state == PCI_D2) in pci_raw_set_power_state()
1123 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_raw_set_power_state()
1124 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_raw_set_power_state()
1125 if (dev->current_state != state) in pci_raw_set_power_state()
1126 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n", in pci_raw_set_power_state()
1127 pci_power_name(dev->current_state), in pci_raw_set_power_state()
1128 pci_power_name(state)); in pci_raw_set_power_state()
1139 * devices in a D3hot state at boot. Consequently, we need to in pci_raw_set_power_state()
1146 if (dev->bus->self) in pci_raw_set_power_state()
1147 pcie_aspm_pm_state_change(dev->bus->self); in pci_raw_set_power_state()
1153 * pci_update_current_state - Read power state of given device and cache it
1155 * @state: State to cache in case the device doesn't have the PM capability
1157 * The power state is read from the PMCSR register, which however is
1160 * reports an incorrect state or the device isn't power manageable by the
1164 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) in pci_update_current_state() argument
1168 dev->current_state = PCI_D3cold; in pci_update_current_state()
1169 } else if (dev->pm_cap) { in pci_update_current_state()
1172 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1173 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); in pci_update_current_state()
1175 dev->current_state = state; in pci_update_current_state()
1180 * pci_refresh_power_state - Refresh the given device's power state data
1183 * Ask the platform to refresh the devices power state information and invoke
1184 * pci_update_current_state() to update its current PCI power state.
1191 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1195 * pci_platform_power_transition - Use platform to change device power state
1197 * @state: State to put the device into.
1199 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) in pci_platform_power_transition() argument
1204 error = platform_pci_set_power_state(dev, state); in pci_platform_power_transition()
1206 pci_update_current_state(dev, state); in pci_platform_power_transition()
1208 error = -ENODEV; in pci_platform_power_transition()
1210 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1211 dev->current_state = PCI_D0; in pci_platform_power_transition()
1219 pm_request_resume(&pci_dev->dev); in pci_resume_one()
1224 * pci_resume_bus - Walk given bus and runtime resume devices on it
1246 * Wait for the device to return a non-CRS completion. Read the in pci_dev_wait()
1254 delay - 1, reset_type); in pci_dev_wait()
1255 return -ENOTTY; in pci_dev_wait()
1260 delay - 1, reset_type); in pci_dev_wait()
1268 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1275 * pci_power_up - Put the given device into D0
1287 if (dev->runtime_d3cold) { in pci_power_up()
1290 * may be powered on into D0uninitialized state, resume them to in pci_power_up()
1293 pci_resume_bus(dev->subordinate); in pci_power_up()
1300 * __pci_dev_set_current_state - Set current state of a PCI device
1302 * @data: pointer to state to be set
1306 pci_power_t state = *(pci_power_t *)data; in __pci_dev_set_current_state() local
1308 dev->current_state = state; in __pci_dev_set_current_state()
1313 * pci_bus_set_current_state - Walk given bus and set current state of devices
1315 * @state: state to be set
1317 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state) in pci_bus_set_current_state() argument
1320 pci_walk_bus(bus, __pci_dev_set_current_state, &state); in pci_bus_set_current_state()
1324 * pci_set_power_state - Set the power state of a PCI device
1326 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1328 * Transition a device to a new power state, using the platform firmware and/or
1332 * -EINVAL if the requested state is invalid.
1333 * -EIO if device does not support PCI PM or its PM capabilities register has a
1334 * wrong version, or device doesn't support the requested state.
1336 * 0 if device already is in the requested state.
1338 * 0 if device's power state has been successfully changed.
1340 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) in pci_set_power_state() argument
1344 /* Bound the state we're entering */ in pci_set_power_state()
1345 if (state > PCI_D3cold) in pci_set_power_state()
1346 state = PCI_D3cold; in pci_set_power_state()
1347 else if (state < PCI_D0) in pci_set_power_state()
1348 state = PCI_D0; in pci_set_power_state()
1349 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) in pci_set_power_state()
1360 if (dev->current_state == state) in pci_set_power_state()
1363 if (state == PCI_D0) in pci_set_power_state()
1370 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in pci_set_power_state()
1377 error = pci_raw_set_power_state(dev, state > PCI_D3hot ? in pci_set_power_state()
1378 PCI_D3hot : state); in pci_set_power_state()
1380 if (pci_platform_power_transition(dev, state)) in pci_set_power_state()
1384 if (state == PCI_D3cold) in pci_set_power_state()
1385 pci_bus_set_current_state(dev->subordinate, PCI_D3cold); in pci_set_power_state()
1392 * pci_choose_state - Choose the power state of a PCI device
1393 * @dev: PCI device to be suspended
1394 * @state: target sleep state for the whole system. This is the value
1397 * Returns PCI power state suitable for given device and given system
1400 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) in pci_choose_state() argument
1404 if (!dev->pm_cap) in pci_choose_state()
1411 switch (state.event) { in pci_choose_state()
1416 /* REVISIT both freeze and pre-thaw "should" use D0 */ in pci_choose_state()
1422 state.event); in pci_choose_state()
1436 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1437 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1465 return -ENOMEM; in pci_save_pcie_state()
1468 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1490 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1512 return -ENOMEM; in pci_save_pcix_state()
1516 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1531 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1555 cap = (u16 *)&save_state->cap.data[0]; in pci_save_ltr_state()
1571 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_ltr_state()
1577 * pci_save_state - save the PCI configuration space of a device before
1586 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1588 i * 4, dev->saved_config_space[i]); in pci_save_state()
1590 dev->state_saved = true; in pci_save_state()
1621 if (retry-- <= 0) in pci_restore_config_dword()
1638 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1640 pdev->saved_config_space[index], in pci_restore_config_space_range()
1646 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1651 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1685 res = pdev->resource + bar_idx; in pci_restore_rebar_state()
1694 * pci_restore_state - Restore the saved state of a PCI device
1699 if (!dev->state_saved) in pci_restore_state()
1725 /* Restore ACS and IOV configuration state */ in pci_restore_state()
1729 dev->state_saved = false; in pci_restore_state()
1739 * pci_store_saved_state - Allocate and return an opaque struct containing
1740 * the device saved state.
1743 * Return NULL if no state or error.
1747 struct pci_saved_state *state; in pci_store_saved_state() local
1752 if (!dev->state_saved) in pci_store_saved_state()
1755 size = sizeof(*state) + sizeof(struct pci_cap_saved_data); in pci_store_saved_state()
1757 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1758 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1760 state = kzalloc(size, GFP_KERNEL); in pci_store_saved_state()
1761 if (!state) in pci_store_saved_state()
1764 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1765 sizeof(state->config_space)); in pci_store_saved_state()
1767 cap = state->cap; in pci_store_saved_state()
1768 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1769 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1770 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
1775 return state; in pci_store_saved_state()
1780 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1782 * @state: Saved state returned from pci_store_saved_state()
1785 struct pci_saved_state *state) in pci_load_saved_state() argument
1789 dev->state_saved = false; in pci_load_saved_state()
1791 if (!state) in pci_load_saved_state()
1794 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
1795 sizeof(state->config_space)); in pci_load_saved_state()
1797 cap = state->cap; in pci_load_saved_state()
1798 while (cap->size) { in pci_load_saved_state()
1801 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
1802 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
1803 return -EINVAL; in pci_load_saved_state()
1805 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
1807 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
1810 dev->state_saved = true; in pci_load_saved_state()
1816 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1819 * @state: Pointer to saved state returned from pci_store_saved_state()
1822 struct pci_saved_state **state) in pci_load_and_free_saved_state() argument
1824 int ret = pci_load_saved_state(dev, *state); in pci_load_and_free_saved_state()
1825 kfree(*state); in pci_load_and_free_saved_state()
1826 *state = NULL; in pci_load_and_free_saved_state()
1844 if (err < 0 && err != -EIO) in do_pci_enable_device()
1856 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
1871 * pci_reenable_device - Resume abandoned device
1880 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
1895 if (!dev->is_busmaster) in pci_enable_bridge()
1914 * Power state could be unknown at this point, either due to a fresh in pci_enable_device_flags()
1915 * boot or a device removal call. So get the current power state in pci_enable_device_flags()
1919 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
1921 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
1930 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
1933 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
1938 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
1943 * pci_enable_device_io - Initialize a device for use with IO space
1946 * Initialize device before it's used by a driver. Ask low-level code
1947 * to enable I/O resources. Wake up the device if it was suspended.
1957 * pci_enable_device_mem - Initialize a device for use with Memory space
1960 * Initialize device before it's used by a driver. Ask low-level code
1961 * to enable Memory resources. Wake up the device if it was suspended.
1971 * pci_enable_device - Initialize device before it's used by a driver.
1974 * Initialize device before it's used by a driver. Ask low-level code
1975 * to enable I/O and memory. Wake up the device if it was suspended.
1988 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1989 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2008 if (dev->msi_enabled) in pcim_release()
2010 if (dev->msix_enabled) in pcim_release()
2014 if (this->region_mask & (1 << i)) in pcim_release()
2017 if (this->mwi) in pcim_release()
2020 if (this->restore_intx) in pcim_release()
2021 pci_intx(dev, this->orig_intx); in pcim_release()
2023 if (this->enabled && !this->pinned) in pcim_release()
2031 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); in get_pci_dr()
2038 return devres_get(&pdev->dev, new_dr, NULL, NULL); in get_pci_dr()
2044 return devres_find(&pdev->dev, pcim_release, NULL, NULL); in find_pci_dr()
2049 * pcim_enable_device - Managed pci_enable_device()
2061 return -ENOMEM; in pcim_enable_device()
2062 if (dr->enabled) in pcim_enable_device()
2067 pdev->is_managed = 1; in pcim_enable_device()
2068 dr->enabled = 1; in pcim_enable_device()
2075 * pcim_pin_device - Pin managed PCI device
2087 WARN_ON(!dr || !dr->enabled); in pcim_pin_device()
2089 dr->pinned = 1; in pcim_pin_device()
2094 * pcibios_add_device - provide arch specific hooks when adding device dev
2107 * pcibios_release_device - provide arch specific hooks when releasing
2118 * pcibios_disable_device - disable arch specific PCI resources for device dev
2128 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2132 * Permits the platform to provide architecture-specific functionality when
2152 * pci_disable_enabled_device - Disable device without updating enable_cnt
2165 * pci_disable_device - Disable PCI device after use
2169 * anymore. This only involves disabling PCI bus-mastering, if active.
2180 dr->enabled = 0; in pci_disable_device()
2182 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2183 "disabling already-disabled device"); in pci_disable_device()
2185 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2190 dev->is_busmaster = 0; in pci_disable_device()
2195 * pcibios_set_pcie_reset_state - set reset state for device dev
2197 * @state: Reset state to enter into
2199 * Set the PCIe reset state for the device. This is the default
2203 enum pcie_reset_state state) in pcibios_set_pcie_reset_state() argument
2205 return -EINVAL; in pcibios_set_pcie_reset_state()
2209 * pci_set_pcie_reset_state - set reset state for device dev
2211 * @state: Reset state to enter into
2213 * Sets the PCI reset state for the device.
2215 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) in pci_set_pcie_reset_state() argument
2217 return pcibios_set_pcie_reset_state(dev, state); in pci_set_pcie_reset_state()
2230 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2239 * pci_check_pme_status - Check if given device has generated PME.
2252 if (!dev->pm_cap) in pci_check_pme_status()
2255 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2274 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2283 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2284 dev->pme_poll = false; in pci_pme_wakeup()
2288 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2294 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2305 * pci_pme_capable - check the capability of PCI device to generate PME#
2307 * @state: PCI state from which device will issue PME#.
2309 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) in pci_pme_capable() argument
2311 if (!dev->pm_cap) in pci_pme_capable()
2314 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2324 if (pme_dev->dev->pme_poll) { in pci_pme_list_scan()
2327 bridge = pme_dev->dev->bus->self; in pci_pme_list_scan()
2329 * If bridge is in low power state, the in pci_pme_list_scan()
2333 if (bridge && bridge->current_state != PCI_D0) in pci_pme_list_scan()
2339 if (pme_dev->dev->current_state == PCI_D3cold) in pci_pme_list_scan()
2342 pci_pme_wakeup(pme_dev->dev, NULL); in pci_pme_list_scan()
2344 list_del(&pme_dev->list); in pci_pme_list_scan()
2358 if (!dev->pme_support) in __pci_pme_active()
2361 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2367 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2371 * pci_pme_restore - Restore PME configuration after config space restore.
2378 if (!dev->pme_support) in pci_pme_restore()
2381 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2382 if (dev->wakeup_prepared) { in pci_pme_restore()
2389 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2393 * pci_pme_active - enable or disable PCI device's PME# function
2409 * periodically walk the list of suspended devices and check in pci_pme_active()
2415 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2424 if (dev->pme_poll) { in pci_pme_active()
2433 pme_dev->dev = dev; in pci_pme_active()
2435 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2444 if (pme_dev->dev == dev) { in pci_pme_active()
2445 list_del(&pme_dev->list); in pci_pme_active()
2459 * __pci_enable_wake - enable PCI device as wakeup event source
2461 * @state: PCI state from which device will issue wakeup events
2465 * When such events involves platform-specific hooks, those hooks are
2473 * -EINVAL is returned if device is not supposed to wake up the system
2475 * the native mechanism fail to enable the generation of wake-up events
2477 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) in __pci_enable_wake() argument
2482 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2485 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2492 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2498 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2507 * the current target state, because that will allow it to in __pci_enable_wake()
2511 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold)) in __pci_enable_wake()
2519 dev->wakeup_prepared = true; in __pci_enable_wake()
2523 dev->wakeup_prepared = false; in __pci_enable_wake()
2530 * pci_enable_wake - change wakeup settings for a PCI device
2532 * @state: PCI state from which device will issue wakeup events
2538 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) in pci_enable_wake() argument
2540 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2541 return -EINVAL; in pci_enable_wake()
2543 return __pci_enable_wake(pci_dev, state, enable); in pci_enable_wake()
2548 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2550 * @enable: True to enable wake-up event generation; false to disable
2553 * and this function allows them to set that up cleanly - pci_enable_wake()
2554 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2559 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2570 * pci_target_state - find an appropriate low power state for a given PCI dev
2574 * Use underlying platform code to find a supported low power state for @dev.
2575 * If the platform can't manage @dev, return the deepest state from which it
2584 * Call the platform to find the target state for the device. in pci_target_state()
2586 pci_power_t state = platform_pci_choose_state(dev); in pci_target_state() local
2588 switch (state) { in pci_target_state()
2598 target_state = state; in pci_target_state()
2604 if (!dev->pm_cap) in pci_target_state()
2608 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2609 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2612 if (dev->current_state == PCI_D3cold) in pci_target_state()
2615 if (wakeup && dev->pme_support) { in pci_target_state()
2616 pci_power_t state = target_state; in pci_target_state() local
2619 * Find the deepest state from which the device can generate in pci_target_state()
2622 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2623 state--; in pci_target_state()
2625 if (state) in pci_target_state()
2626 return state; in pci_target_state()
2627 else if (dev->pme_support & 1) in pci_target_state()
2635 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2636 * into a sleep state
2639 * Choose the power state appropriate for the device depending on whether
2641 * (PCI_D3hot is the default) and put the device into that state.
2645 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep()
2650 return -EIO; in pci_prepare_to_sleep()
2654 * Lake) where the power drawn while suspended can be significantly in pci_prepare_to_sleep()
2656 * port to enter a lower-power PM state and the SoC to reach a in pci_prepare_to_sleep()
2657 * lower-power idle state as a whole. in pci_prepare_to_sleep()
2676 * pci_back_from_sleep - turn PCI device on during system-wide transition
2677 * into working state
2680 * Disable device's system wake-up capability and put it into D0.
2690 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2691 * @dev: PCI device being suspended.
2693 * Prepare @dev to generate wake-up events at run time and put it into a low
2694 * power state.
2701 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2703 return -EIO; in pci_finish_runtime_suspend()
2705 dev->runtime_d3cold = target_state == PCI_D3cold; in pci_finish_runtime_suspend()
2709 * Lake) where the power drawn while suspended can be significantly in pci_finish_runtime_suspend()
2711 * port to enter a lower-power PM state and the SoC to reach a in pci_finish_runtime_suspend()
2712 * lower-power idle state as a whole. in pci_finish_runtime_suspend()
2724 dev->runtime_d3cold = false; in pci_finish_runtime_suspend()
2731 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2734 * Return true if the device itself is capable of generating wake-up events
2736 * PME and one of its upstream bridges can generate wake-up events.
2740 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2742 if (!dev->pme_support) in pci_dev_run_wake()
2745 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2749 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2752 while (bus->parent) { in pci_dev_run_wake()
2753 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2755 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2758 bus = bus->parent; in pci_dev_run_wake()
2762 if (bus->bridge) in pci_dev_run_wake()
2763 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2770 * pci_dev_need_resume - Check if it is necessary to resume the device.
2773 * Return 'true' if the device is not runtime-suspended or it has to be
2775 * suspend, or the current power state of it is not suitable for the upcoming
2776 * (system-wide) transition.
2780 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2793 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2795 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2799 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2802 * If the device is suspended and it is not configured for system wakeup,
2805 * Note that if the device's power state is D3cold and the platform check in
2811 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2813 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2816 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
2819 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2823 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2826 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2832 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
2837 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2839 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2842 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2847 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
2848 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2854 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
2860 * registers are still accessible for devices suspended but in pci_config_pm_runtime_get()
2863 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
2869 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
2870 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
2886 .ident = "X299 DESIGNARE EX-CF",
2889 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2897 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2917 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
2919 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
2926 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
2938 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
2961 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
2964 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
2976 * pci_bridge_d3_update - Update bridge D3 capabilities
2985 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
2997 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
3017 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
3018 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
3021 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
3022 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
3029 * pci_d3cold_enable - Enable D3cold for device
3038 if (dev->no_d3cold) { in pci_d3cold_enable()
3039 dev->no_d3cold = false; in pci_d3cold_enable()
3046 * pci_d3cold_disable - Disable D3cold for device
3055 if (!dev->no_d3cold) { in pci_d3cold_disable()
3056 dev->no_d3cold = true; in pci_d3cold_disable()
3063 * pci_pm_init - Initialize PM functions of given PCI device
3072 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3073 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3074 pm_runtime_enable(&dev->dev); in pci_pm_init()
3075 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3076 dev->wakeup_prepared = false; in pci_pm_init()
3078 dev->pm_cap = 0; in pci_pm_init()
3079 dev->pme_support = 0; in pci_pm_init()
3094 dev->pm_cap = pm; in pci_pm_init()
3095 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3096 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3097 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3098 dev->d3cold_allowed = true; in pci_pm_init()
3100 dev->d1_support = false; in pci_pm_init()
3101 dev->d2_support = false; in pci_pm_init()
3104 dev->d1_support = true; in pci_pm_init()
3106 dev->d2_support = true; in pci_pm_init()
3108 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3110 dev->d1_support ? " D1" : "", in pci_pm_init()
3111 dev->d2_support ? " D2" : ""); in pci_pm_init()
3122 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; in pci_pm_init()
3123 dev->pme_poll = true; in pci_pm_init()
3125 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3128 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3135 dev->imm_ready = 1; in pci_pm_init()
3165 return &dev->resource[bei]; in pci_ea_get_resource()
3169 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3170 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3173 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3231 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3240 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3250 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3272 if (ent_size != ent_offset - offset) { in pci_ea_read()
3274 ent_size, ent_offset - offset); in pci_ea_read()
3278 res->name = pci_name(dev); in pci_ea_read()
3279 res->start = start; in pci_ea_read()
3280 res->end = end; in pci_ea_read()
3281 res->flags = flags; in pci_ea_read()
3291 bei - PCI_EA_BEI_VF_BAR0, res, prop); in pci_ea_read()
3314 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3321 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3332 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3336 * _pci_add_cap_save_buffer - allocate buffer for saving given
3359 return -ENOMEM; in _pci_add_cap_save_buffer()
3361 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3362 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3363 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3380 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3394 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3409 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3414 * pci_configure_ari - enable or disable ARI forwarding
3425 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3428 bridge = dev->bus->self; in pci_configure_ari()
3439 bridge->ari_enabled = 1; in pci_configure_ari()
3443 bridge->ari_enabled = 0; in pci_configure_ari()
3452 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3459 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3469 * pci_acs_enabled - test ACS against required flags for a given device
3479 * opportunity for peer-to-peer access. We therefore return 'true'
3493 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3502 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3504 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3518 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3519 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3526 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3535 if (!pdev->multifunction) in pci_acs_enabled()
3549 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3568 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3571 parent = pdev->bus->self; in pci_acs_path_enabled()
3578 * pci_acs_init - Initialize ACS if hardware supports it
3583 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3595 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3600 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3601 * Returns -ENOENT if no ctrl register for the BAR could be found.
3610 return -ENOTSUPP; in pci_rebar_find_pos()
3625 return -ENOENT; in pci_rebar_find_pos()
3629 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3649 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3658 * pci_rebar_get_current_size - get the current size of a BAR
3679 * pci_rebar_set_size - set a new size for a BAR
3704 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3713 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3718 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3723 return -EINVAL; in pci_enable_atomic_ops_to_root()
3729 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3738 return -EINVAL; in pci_enable_atomic_ops_to_root()
3741 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3742 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3751 return -EINVAL; in pci_enable_atomic_ops_to_root()
3757 return -EINVAL; in pci_enable_atomic_ops_to_root()
3766 return -EINVAL; in pci_enable_atomic_ops_to_root()
3769 bus = bus->parent; in pci_enable_atomic_ops_to_root()
3779 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3784 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3785 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3793 if (pci_ari_enabled(dev->bus)) in pci_swizzle_interrupt_pin()
3796 slot = PCI_SLOT(dev->devfn); in pci_swizzle_interrupt_pin()
3798 return (((pin - 1) + slot) % 4) + 1; in pci_swizzle_interrupt_pin()
3805 pin = dev->pin; in pci_get_interrupt_pin()
3807 return -1; in pci_get_interrupt_pin()
3809 while (!pci_is_root_bus(dev->bus)) { in pci_get_interrupt_pin()
3811 dev = dev->bus->self; in pci_get_interrupt_pin()
3818 * pci_common_swizzle - swizzle INTx all the way to root bridge
3822 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3829 while (!pci_is_root_bus(dev->bus)) { in pci_common_swizzle()
3831 dev = dev->bus->self; in pci_common_swizzle()
3834 return PCI_SLOT(dev->devfn); in pci_common_swizzle()
3839 * pci_release_region - Release a PCI bar
3863 dr->region_mask &= ~(1 << bar); in pci_release_region()
3868 * __pci_request_region - Reserved PCI I/O and memory resource
3907 dr->region_mask |= 1 << bar; in __pci_request_region()
3913 &pdev->resource[bar]); in __pci_request_region()
3914 return -EBUSY; in __pci_request_region()
3918 * pci_request_region - Reserve PCI I/O and memory resource
3938 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3967 while (--i >= 0) in __pci_request_selected_regions()
3971 return -EBUSY; in __pci_request_selected_regions()
3976 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3997 * pci_release_regions - Release reserved PCI I/O and memory resources
4008 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
4013 * pci_request_regions - Reserve PCI I/O and memory resources
4028 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions()
4033 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4050 ((1 << PCI_STD_NUM_BARS) - 1), res_name); in pci_request_regions_exclusive()
4066 return -EINVAL; in pci_register_io_range()
4070 return -ENOMEM; in pci_register_io_range()
4072 range->fwnode = fwnode; in pci_register_io_range()
4073 range->size = size; in pci_register_io_range()
4074 range->hw_start = addr; in pci_register_io_range()
4075 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4082 if (ret == -EEXIST) in pci_register_io_range()
4110 return (unsigned long)-1; in pci_address_to_pio()
4117 * pci_remap_iospace - Remap the memory mapped I/O space
4129 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4131 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4132 return -EINVAL; in pci_remap_iospace()
4134 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4135 return -EINVAL; in pci_remap_iospace()
4145 return -ENODEV; in pci_remap_iospace()
4151 * pci_unmap_iospace - Unmap the memory mapped I/O space
4161 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4176 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4192 return -ENOMEM; in devm_pci_remap_iospace()
4207 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4237 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4251 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4266 return IOMEM_ERR_PTR(-EINVAL); in devm_pci_remap_cfg_resource()
4271 if (res->name) in devm_pci_remap_cfg_resource()
4273 res->name); in devm_pci_remap_cfg_resource()
4277 return IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4279 if (!devm_request_mem_region(dev, res->start, size, name)) { in devm_pci_remap_cfg_resource()
4281 return IOMEM_ERR_PTR(-EBUSY); in devm_pci_remap_cfg_resource()
4284 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size); in devm_pci_remap_cfg_resource()
4287 devm_release_mem_region(dev, res->start, size); in devm_pci_remap_cfg_resource()
4288 dest_ptr = IOMEM_ERR_PTR(-ENOMEM); in devm_pci_remap_cfg_resource()
4309 dev->is_busmaster = enable; in __pci_set_master()
4313 * pcibios_setup - process "pci=" kernel boot arguments
4325 * pcibios_set_master - enable PCI bus-mastering for device dev
4328 * Enables PCI bus-mastering for the device. This is the default
4352 * pci_set_master - enables bus-mastering for device dev
4355 * Enables bus-mastering on the device and calls pcibios_set_master()
4366 * pci_clear_master - disables bus-mastering for device dev
4376 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4381 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4383 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4390 return -EINVAL; in pci_set_cacheline_size()
4409 return -EINVAL; in pci_set_cacheline_size()
4414 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4417 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4419 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4435 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4445 * pcim_set_mwi - a device-managed pci_set_mwi()
4450 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4458 return -ENOMEM; in pcim_set_mwi()
4460 dr->mwi = 1; in pcim_set_mwi()
4466 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4469 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4472 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4485 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4488 * Disables PCI Memory-Write-Invalidate transaction on the device
4505 * pci_disable_parity - disable parity checking for device
4522 * pci_intx - enables/disables PCI INTx for device dev
4545 if (dr && !dr->restore_intx) { in pci_intx()
4546 dr->restore_intx = 1; in pci_intx()
4547 dr->orig_intx = !enable; in pci_intx()
4555 struct pci_bus *bus = dev->bus; in pci_check_and_set_intx_mask()
4571 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword); in pci_check_and_set_intx_mask()
4590 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd); in pci_check_and_set_intx_mask()
4599 * pci_check_and_mask_intx - mask INTx on pending interrupt
4612 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4626 * pci_wait_for_pending_transaction - wait for pending transaction
4642 * pcie_flr - initiate a PCIe function level reset
4655 if (dev->imm_ready) in pcie_flr()
4670 * pcie_reset_flr - initiate a PCIe function level reset
4678 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_reset_flr()
4679 return -ENOTTY; in pcie_reset_flr()
4681 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) in pcie_reset_flr()
4682 return -ENOTTY; in pcie_reset_flr()
4698 return -ENOTTY; in pci_af_flr()
4700 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4701 return -ENOTTY; in pci_af_flr()
4705 return -ENOTTY; in pci_af_flr()
4711 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4721 if (dev->imm_ready) in pci_af_flr()
4736 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4742 * PCI_D0. If that's the case and the device is not in a low-power state
4746 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4754 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4755 return -ENOTTY; in pci_pm_reset()
4757 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4759 return -ENOTTY; in pci_pm_reset()
4764 if (dev->current_state != PCI_D0) in pci_pm_reset()
4765 return -EINVAL; in pci_pm_reset()
4769 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4774 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4777 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
4781 * pcie_wait_for_link_delay - Wait until link is active or inactive
4799 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
4823 timeout -= 10; in pcie_wait_for_link_delay()
4832 * pcie_wait_for_link - Wait until link is active or inactive
4856 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
4857 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
4858 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4859 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
4860 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4867 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4885 if (!pci_is_bridge(dev) || !dev->bridge_d3) in pci_bridge_wait_for_secondary_bus()
4892 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
4896 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
4902 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
4908 child = list_first_entry(&dev->subordinate->devices, struct pci_dev, in pci_bridge_wait_for_secondary_bus()
4913 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
4984 * be re-initialized. PCIe has some ways to shorten this, in pci_reset_secondary_bus()
4996 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5000 * Devices on the secondary bus are left in power-on state.
5014 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
5015 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
5016 return -ENOTTY; in pci_parent_bus_reset()
5018 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
5020 return -ENOTTY; in pci_parent_bus_reset()
5025 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
5030 int rc = -ENOTTY; in pci_reset_hotplug_slot()
5032 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
5035 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
5036 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
5038 module_put(hotplug->owner); in pci_reset_hotplug_slot()
5045 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
5046 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
5047 return -ENOTTY; in pci_dev_reset_slot_function()
5049 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
5057 if (rc != -ENOTTY) in pci_reset_bus_function()
5066 device_lock(&dev->dev); in pci_dev_lock()
5073 if (device_trylock(&dev->dev)) in pci_dev_trylock()
5084 device_unlock(&dev->dev); in pci_dev_unlock()
5092 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
5095 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
5096 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5099 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5100 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5103 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5105 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5112 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5114 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5115 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5123 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5128 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5129 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5132 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5133 err_handler->reset_done(dev); in pci_dev_restore()
5136 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5155 m = pdev->reset_methods[i]; in reset_method_show()
5191 pdev->reset_methods[0] = 0; in reset_method_store()
5203 return -ENOMEM; in reset_method_store()
5223 if (n == PCI_NUM_RESET_METHODS - 1) { in reset_method_store()
5233 /* Warn if dev-specific supported but not highest priority */ in reset_method_store()
5236 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user"); in reset_method_store()
5237 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods)); in reset_method_store()
5244 return -EINVAL; in reset_method_store()
5261 return a->mode; in pci_dev_reset_method_attr_is_visible()
5270 * __pci_reset_function_locked - reset a PCI device function while holding
5291 int i, m, rc = -ENOTTY; in __pci_reset_function_locked()
5296 * A reset method returns -ENOTTY if it doesn't support this device and in __pci_reset_function_locked()
5304 m = dev->reset_methods[i]; in __pci_reset_function_locked()
5306 return -ENOTTY; in __pci_reset_function_locked()
5311 if (rc != -ENOTTY) in __pci_reset_function_locked()
5315 return -ENOTTY; in __pci_reset_function_locked()
5320 * pci_init_reset_methods - check whether device can be safely reset
5325 * other functions in the same device. The PCI device must be in D0-D3hot
5326 * state.
5343 dev->reset_methods[i++] = m; in pci_init_reset_methods()
5344 else if (rc != -ENOTTY) in pci_init_reset_methods()
5348 dev->reset_methods[i] = 0; in pci_init_reset_methods()
5352 * pci_reset_function - quiesce and reset a PCI device function
5360 * clears all the state associated with the device. This function differs
5361 * from __pci_reset_function_locked() in that it saves and restores device state
5372 return -ENOTTY; in pci_reset_function()
5387 * pci_reset_function_locked - quiesce and reset a PCI device function
5395 * clears all the state associated with the device. This function differs
5396 * from __pci_reset_function_locked() in that it saves and restores device state
5408 return -ENOTTY; in pci_reset_function_locked()
5421 * pci_try_reset_function - quiesce and reset a PCI device function
5424 * Same as above, except return -EAGAIN if unable to lock device.
5431 return -ENOTTY; in pci_try_reset_function()
5434 return -EAGAIN; in pci_try_reset_function()
5451 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resetable()
5454 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resetable()
5455 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resetable()
5456 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) in pci_bus_resetable()
5468 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5470 if (dev->subordinate) in pci_bus_lock()
5471 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5480 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5481 if (dev->subordinate) in pci_bus_unlock()
5482 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5492 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5495 if (dev->subordinate) { in pci_bus_trylock()
5496 if (!pci_bus_trylock(dev->subordinate)) { in pci_bus_trylock()
5505 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5506 if (dev->subordinate) in pci_bus_trylock()
5507 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5518 if (slot->bus->self && in pci_slot_resetable()
5519 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resetable()
5522 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resetable()
5523 if (!dev->slot || dev->slot != slot) in pci_slot_resetable()
5525 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resetable()
5526 (dev->subordinate && !pci_bus_resetable(dev->subordinate))) in pci_slot_resetable()
5538 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5539 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5542 if (dev->subordinate) in pci_slot_lock()
5543 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5552 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5553 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5555 if (dev->subordinate) in pci_slot_unlock()
5556 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5566 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5567 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5571 if (dev->subordinate) { in pci_slot_trylock()
5572 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5582 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5583 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5585 if (dev->subordinate) in pci_slot_trylock()
5586 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5600 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5602 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5603 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5616 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5618 if (dev->subordinate) in pci_bus_restore_locked()
5619 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5631 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5632 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5635 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5636 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5649 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5650 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5653 if (dev->subordinate) in pci_slot_restore_locked()
5654 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5663 return -ENOTTY; in pci_slot_reset()
5670 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5679 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5691 * __pci_reset_slot - Try to reset a PCI slot
5703 * Same as above except return -EAGAIN if the slot cannot be locked
5716 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); in __pci_reset_slot()
5720 rc = -EAGAIN; in __pci_reset_slot()
5729 if (!bus->self || !pci_bus_resetable(bus)) in pci_bus_reset()
5730 return -ENOTTY; in pci_bus_reset()
5739 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
5747 * pci_bus_error_reset - reset the bridge's subordinate bus
5756 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
5760 return -ENOTTY; in pci_bus_error_reset()
5763 if (list_empty(&bus->slots)) in pci_bus_error_reset()
5766 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5770 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5778 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); in pci_bus_error_reset()
5782 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5794 * __pci_reset_bus - Try to reset a PCI bus
5797 * Same as above except return -EAGAIN if the bus cannot be locked
5810 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
5814 rc = -EAGAIN; in __pci_reset_bus()
5820 * pci_reset_bus - Try to reset a PCI bus
5823 * Same as above except return -EAGAIN if the bus cannot be locked
5827 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
5828 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
5833 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5846 return -EINVAL; in pcix_get_max_mmrbc()
5849 return -EINVAL; in pcix_get_max_mmrbc()
5856 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5869 return -EINVAL; in pcix_get_mmrbc()
5872 return -EINVAL; in pcix_get_mmrbc()
5879 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5894 return -EINVAL; in pcix_set_mmrbc()
5896 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
5900 return -EINVAL; in pcix_set_mmrbc()
5903 return -EINVAL; in pcix_set_mmrbc()
5906 return -E2BIG; in pcix_set_mmrbc()
5909 return -EINVAL; in pcix_set_mmrbc()
5913 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
5914 return -EIO; in pcix_set_mmrbc()
5919 return -EIO; in pcix_set_mmrbc()
5926 * pcie_get_readrq - get PCI Express read request size
5942 * pcie_set_readrq - set PCI Express maximum memory read request
5955 return -EINVAL; in pcie_set_readrq()
5969 v = (ffs(rq) - 8) << 12; in pcie_set_readrq()
5979 * pcie_get_mps - get PCI Express maximum payload size
5995 * pcie_set_mps - set PCI Express maximum payload size
6008 return -EINVAL; in pcie_set_mps()
6010 v = ffs(mps) - 8; in pcie_set_mps()
6011 if (v > dev->pcie_mpss) in pcie_set_mps()
6012 return -EINVAL; in pcie_set_mps()
6023 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6081 * pcie_get_speed_cap - query for the PCI device's link speed capability
6102 /* PCIe r3.0-compliant */ in pcie_get_speed_cap()
6117 * pcie_get_width_cap - query for the PCI device's link width capability
6136 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6158 * __pcie_print_link_status - Report the PCI device's link speed and width
6191 * pcie_print_link_status - Report the PCI device's link speed and width
6203 * pci_select_bars - Make BAR mask from the type of resource
6237 * pci_set_vga_state - set VGA decode state on device and parents if requested
6271 bus = dev->bus; in pci_set_vga_state()
6273 bridge = bus->self; in pci_set_vga_state()
6284 bus = bus->parent; in pci_set_vga_state()
6297 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6301 return adev->power.flags.power_resources && in pci_pr3_present()
6302 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6308 * pci_add_dma_alias - Add a DMA devfn alias for a device
6313 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6314 * which is used to program permissible bus-devfn source addresses for DMA
6317 * from their logical bus-devfn. Examples include device quirks where the
6318 * device simply uses the wrong devfn, as well as non-transparent bridges
6331 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6332 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6334 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6335 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6336 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6341 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6354 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6355 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6356 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6357 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6368 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6374 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6376 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6379 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6384 * pci_real_dma_dev - Get PCI DMA device for PCI device
6387 * Permits the platform to provide architecture-specific functionality to
6404 * Arches that don't want to expose struct resource to userland as-is in
6411 *start = rsrc->start; in pci_resource_to_user()
6412 *end = rsrc->end; in pci_resource_to_user()
6419 * pci_specified_resource_alignment - get resource alignment specified by user.
6483 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6486 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6489 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6515 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and in pci_request_resource_alignment()
6516 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6531 r->start = 0; in pci_request_resource_alignment()
6532 r->end = align - 1; in pci_request_resource_alignment()
6534 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6535 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6536 r->start = align; in pci_request_resource_alignment()
6537 r->end = r->start + size - 1; in pci_request_resource_alignment()
6539 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6546 * Later on, the kernel will assign page-aligned memory resource back
6558 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6560 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6563 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6571 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6572 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6589 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6591 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6592 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6594 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6595 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6596 r->start = 0; in pci_reassigndev_resource_alignment()
6619 if (count >= (PAGE_SIZE - 1)) in resource_alignment_store()
6620 return -EINVAL; in resource_alignment_store()
6624 return -ENOMEM; in resource_alignment_store()
6662 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6671 static int use_dt_domains = -1; in of_pci_bus_find_domain_nr()
6672 int domain = -1; in of_pci_bus_find_domain_nr()
6675 domain = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
6700 * invalidating the domain value (domain = -1) and printing a in of_pci_bus_find_domain_nr()
6710 pr_err("Node %pOF has ", parent->of_node); in of_pci_bus_find_domain_nr()
6711 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n"); in of_pci_bus_find_domain_nr()
6712 domain = -1; in of_pci_bus_find_domain_nr()
6726 * pci_ext_cfg_avail - can we access extended PCI config space?