137 	if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&  in pcie_wait_cmd()
138 	    ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)  in pcie_wait_cmd()
145 			  ctrl->slot_ctrl,  in pcie_wait_cmd()
158 	u16 slot_ctrl_orig, slot_ctrl;  in pcie_do_write_cmd()  local
167 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pcie_do_write_cmd()
168 	if (slot_ctrl == (u16) ~0) {  in pcie_do_write_cmd()
173 	slot_ctrl_orig = slot_ctrl;  in pcie_do_write_cmd()
174 	slot_ctrl &= ~mask;  in pcie_do_write_cmd()
175 	slot_ctrl |= (cmd & mask);  in pcie_do_write_cmd()
178 	ctrl->slot_ctrl = slot_ctrl;  in pcie_do_write_cmd()
179 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);  in pcie_do_write_cmd()
190 	    (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))  in pcie_do_write_cmd()
357 	u16 slot_ctrl;  in pciehp_get_raw_indicator_status()  local
360 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_raw_indicator_status()
362 	*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;  in pciehp_get_raw_indicator_status()
370 	u16 slot_ctrl;  in pciehp_get_attention_status()  local
373 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_attention_status()
376 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);  in pciehp_get_attention_status()
378 	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {  in pciehp_get_attention_status()
399 	u16 slot_ctrl;  in pciehp_get_power_status()  local
401 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);  in pciehp_get_power_status()
403 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);  in pciehp_get_power_status()
405 	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {  in pciehp_get_power_status()
604 	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))  in pciehp_isr()