Lines Matching +full:ecam +full:- +full:based
1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
22 #include <linux/pci-ecam.h>
34 /* Egress - Bridge translation registers */
44 /* Ingress - address translations */
52 /* Rxed msg fifo - Interrupt status registers */
179 return readl(pcie->breg_base + off); in nwl_bridge_readl()
184 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
189 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
196 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
203 struct device *dev = pcie->dev; in nwl_wait_for_link()
214 return -ETIMEDOUT; in nwl_wait_for_link()
219 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device()
233 * nwl_pcie_map_bus - Get configuration base
245 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus()
250 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in nwl_pcie_map_bus()
263 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
291 dev_err(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
300 dev_err(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
330 generic_handle_domain_irq(pcie->legacy_irq_domain, bit); in nwl_pcie_leg_handler()
342 msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
347 generic_handle_domain_irq(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
379 mask = 1 << (data->hwirq - 1); in nwl_mask_leg_irq()
380 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
383 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
393 mask = 1 << (data->hwirq - 1); in nwl_unmask_leg_irq()
394 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
397 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
412 irq_set_chip_data(irq, domain->host_data); in nwl_legacy_map()
442 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
444 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
445 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
446 msg->data = data->hwirq; in nwl_compose_msi_msg()
452 return -EINVAL; in nwl_msi_set_affinity()
464 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc()
465 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
469 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
470 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
473 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
474 return -ENOSPC; in nwl_irq_domain_alloc()
479 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
482 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
491 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
493 mutex_lock(&msi->lock); in nwl_irq_domain_free()
494 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
496 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
507 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
508 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in nwl_pcie_init_msi_irq_domain()
509 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
511 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, in nwl_pcie_init_msi_irq_domain()
513 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
515 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
517 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in nwl_pcie_init_msi_irq_domain()
519 msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
520 if (!msi->msi_domain) { in nwl_pcie_init_msi_irq_domain()
522 irq_domain_remove(msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
523 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
531 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
532 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
538 return -EINVAL; in nwl_pcie_init_irq_domain()
541 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, in nwl_pcie_init_irq_domain()
546 if (!pcie->legacy_irq_domain) { in nwl_pcie_init_irq_domain()
548 return -ENOMEM; in nwl_pcie_init_irq_domain()
551 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
558 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
560 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
565 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
567 msi->bitmap = kzalloc(size, GFP_KERNEL); in nwl_pcie_enable_msi()
568 if (!msi->bitmap) in nwl_pcie_enable_msi()
569 return -ENOMEM; in nwl_pcie_enable_msi()
572 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
573 if (msi->irq_msi1 < 0) { in nwl_pcie_enable_msi()
574 ret = -EINVAL; in nwl_pcie_enable_msi()
578 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
582 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
583 if (msi->irq_msi0 < 0) { in nwl_pcie_enable_msi()
584 ret = -EINVAL; in nwl_pcie_enable_msi()
588 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
595 ret = -EIO; in nwl_pcie_enable_msi()
608 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
636 kfree(msi->bitmap); in nwl_pcie_enable_msi()
637 msi->bitmap = NULL; in nwl_pcie_enable_msi()
643 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
655 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
657 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
676 if (of_dma_is_coherent(dev->of_node)) in nwl_pcie_bridge_init()
686 dev_err(dev, "ECAM is not present\n"); in nwl_pcie_bridge_init()
690 /* Enable ECAM */ in nwl_pcie_bridge_init()
695 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), in nwl_pcie_bridge_init()
698 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
700 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
705 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; in nwl_pcie_bridge_init()
709 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); in nwl_pcie_bridge_init()
710 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); in nwl_pcie_bridge_init()
718 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
719 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
720 return -EINVAL; in nwl_pcie_bridge_init()
722 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
727 pcie->irq_misc); in nwl_pcie_bridge_init()
762 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
766 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
767 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
768 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
769 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
772 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
773 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
774 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
775 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
778 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
779 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
780 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
781 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
784 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
785 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
786 return pcie->irq_intx; in nwl_pcie_parse_dt()
788 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
795 { .compatible = "xlnx,nwl-pcie-2.11", },
801 struct device *dev = &pdev->dev; in nwl_pcie_probe()
808 return -ENODEV; in nwl_pcie_probe()
812 pcie->dev = dev; in nwl_pcie_probe()
813 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; in nwl_pcie_probe()
821 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
822 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
823 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
825 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
843 bridge->sysdata = pcie; in nwl_pcie_probe()
844 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
859 .name = "nwl-pcie",