Lines Matching +full:generic +full:- +full:pciecfg
1 // SPDX-License-Identifier: GPL-2.0
74 /* PCIe V2 per-port registers */
127 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
145 * struct mtk_pcie_soc - differentiate between host generations
165 * struct mtk_pcie_port - PCIe port information
209 * struct mtk_pcie - PCIe host information
213 * @free_ck: free-run reference clock
214 * @mem: non-prefetchable memory resource
216 * @soc: pointer to SoC-dependent operations
230 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerdown()
232 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_subsys_powerdown()
240 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_port_free()
241 struct device *dev = pcie->dev; in mtk_pcie_port_free()
243 devm_iounmap(dev, port->base); in mtk_pcie_port_free()
244 list_del(&port->list); in mtk_pcie_port_free()
252 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mtk_pcie_put_resources()
253 phy_power_off(port->phy); in mtk_pcie_put_resources()
254 phy_exit(port->phy); in mtk_pcie_put_resources()
255 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_put_resources()
256 clk_disable_unprepare(port->obff_ck); in mtk_pcie_put_resources()
257 clk_disable_unprepare(port->axi_ck); in mtk_pcie_put_resources()
258 clk_disable_unprepare(port->aux_ck); in mtk_pcie_put_resources()
259 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_put_resources()
260 clk_disable_unprepare(port->sys_ck); in mtk_pcie_put_resources()
272 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, in mtk_pcie_check_cfg_cpld()
278 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) in mtk_pcie_check_cfg_cpld()
291 port->base + PCIE_CFG_HEADER0); in mtk_pcie_hw_rd_cfg()
292 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_rd_cfg()
294 port->base + PCIE_CFG_HEADER2); in mtk_pcie_hw_rd_cfg()
297 tmp = readl(port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_rd_cfg()
299 writel(tmp, port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_rd_cfg()
306 *val = readl(port->base + PCIE_CFG_RDATA); in mtk_pcie_hw_rd_cfg()
321 port->base + PCIE_CFG_HEADER0); in mtk_pcie_hw_wr_cfg()
322 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_wr_cfg()
324 port->base + PCIE_CFG_HEADER2); in mtk_pcie_hw_wr_cfg()
328 writel(val, port->base + PCIE_CFG_WDATA); in mtk_pcie_hw_wr_cfg()
331 val = readl(port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_wr_cfg()
333 writel(val, port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_wr_cfg()
342 struct mtk_pcie *pcie = bus->sysdata; in mtk_pcie_find_port()
350 while (bus && bus->number) { in mtk_pcie_find_port()
351 dev = bus->self; in mtk_pcie_find_port()
352 bus = dev->bus; in mtk_pcie_find_port()
353 devfn = dev->devfn; in mtk_pcie_find_port()
356 list_for_each_entry(port, &pcie->ports, list) in mtk_pcie_find_port()
357 if (port->slot == PCI_SLOT(devfn)) in mtk_pcie_find_port()
367 u32 bn = bus->number; in mtk_pcie_config_read()
387 u32 bn = bus->number; in mtk_pcie_config_write()
406 /* MT2712/MT7622 only support 32-bit MSI addresses */ in mtk_compose_msi_msg()
407 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); in mtk_compose_msi_msg()
408 msg->address_hi = 0; in mtk_compose_msi_msg()
409 msg->address_lo = lower_32_bits(addr); in mtk_compose_msi_msg()
411 msg->data = data->hwirq; in mtk_compose_msi_msg()
413 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", in mtk_compose_msi_msg()
414 (int)data->hwirq, msg->address_hi, msg->address_lo); in mtk_compose_msi_msg()
420 return -EINVAL; in mtk_msi_set_affinity()
426 u32 hwirq = data->hwirq; in mtk_msi_ack_irq()
428 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); in mtk_msi_ack_irq()
441 struct mtk_pcie_port *port = domain->host_data; in mtk_pcie_irq_domain_alloc()
445 mutex_lock(&port->lock); in mtk_pcie_irq_domain_alloc()
447 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); in mtk_pcie_irq_domain_alloc()
449 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_alloc()
450 return -ENOSPC; in mtk_pcie_irq_domain_alloc()
453 __set_bit(bit, port->msi_irq_in_use); in mtk_pcie_irq_domain_alloc()
455 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_alloc()
458 domain->host_data, handle_edge_irq, in mtk_pcie_irq_domain_alloc()
470 mutex_lock(&port->lock); in mtk_pcie_irq_domain_free()
472 if (!test_bit(d->hwirq, port->msi_irq_in_use)) in mtk_pcie_irq_domain_free()
473 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", in mtk_pcie_irq_domain_free()
474 d->hwirq); in mtk_pcie_irq_domain_free()
476 __clear_bit(d->hwirq, port->msi_irq_in_use); in mtk_pcie_irq_domain_free()
478 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_free()
503 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); in mtk_pcie_allocate_msi_domains()
505 mutex_init(&port->lock); in mtk_pcie_allocate_msi_domains()
507 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, in mtk_pcie_allocate_msi_domains()
509 if (!port->inner_domain) { in mtk_pcie_allocate_msi_domains()
510 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); in mtk_pcie_allocate_msi_domains()
511 return -ENOMEM; in mtk_pcie_allocate_msi_domains()
514 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, in mtk_pcie_allocate_msi_domains()
515 port->inner_domain); in mtk_pcie_allocate_msi_domains()
516 if (!port->msi_domain) { in mtk_pcie_allocate_msi_domains()
517 dev_err(port->pcie->dev, "failed to create MSI domain\n"); in mtk_pcie_allocate_msi_domains()
518 irq_domain_remove(port->inner_domain); in mtk_pcie_allocate_msi_domains()
519 return -ENOMEM; in mtk_pcie_allocate_msi_domains()
530 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); in mtk_pcie_enable_msi()
532 writel(val, port->base + PCIE_IMSI_ADDR); in mtk_pcie_enable_msi()
534 val = readl(port->base + PCIE_INT_MASK); in mtk_pcie_enable_msi()
536 writel(val, port->base + PCIE_INT_MASK); in mtk_pcie_enable_msi()
543 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mtk_pcie_irq_teardown()
544 irq_set_chained_handler_and_data(port->irq, NULL, NULL); in mtk_pcie_irq_teardown()
546 if (port->irq_domain) in mtk_pcie_irq_teardown()
547 irq_domain_remove(port->irq_domain); in mtk_pcie_irq_teardown()
550 if (port->msi_domain) in mtk_pcie_irq_teardown()
551 irq_domain_remove(port->msi_domain); in mtk_pcie_irq_teardown()
552 if (port->inner_domain) in mtk_pcie_irq_teardown()
553 irq_domain_remove(port->inner_domain); in mtk_pcie_irq_teardown()
556 irq_dispose_mapping(port->irq); in mtk_pcie_irq_teardown()
564 irq_set_chip_data(irq, domain->host_data); in mtk_pcie_intx_map()
576 struct device *dev = port->pcie->dev; in mtk_pcie_init_irq_domain()
584 return -ENODEV; in mtk_pcie_init_irq_domain()
587 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, in mtk_pcie_init_irq_domain()
590 if (!port->irq_domain) { in mtk_pcie_init_irq_domain()
592 return -ENODEV; in mtk_pcie_init_irq_domain()
613 status = readl(port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
617 writel(1 << bit, port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
618 generic_handle_domain_irq(port->irq_domain, in mtk_pcie_intr_handler()
619 bit - INTX_SHIFT); in mtk_pcie_intr_handler()
627 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { in mtk_pcie_intr_handler()
629 generic_handle_domain_irq(port->inner_domain, bit); in mtk_pcie_intr_handler()
632 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
642 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_setup_irq()
643 struct device *dev = pcie->dev; in mtk_pcie_setup_irq()
653 if (of_find_property(dev->of_node, "interrupt-names", NULL)) in mtk_pcie_setup_irq()
654 port->irq = platform_get_irq_byname(pdev, "pcie_irq"); in mtk_pcie_setup_irq()
656 port->irq = platform_get_irq(pdev, port->slot); in mtk_pcie_setup_irq()
658 if (port->irq < 0) in mtk_pcie_setup_irq()
659 return port->irq; in mtk_pcie_setup_irq()
661 irq_set_chained_handler_and_data(port->irq, in mtk_pcie_setup_irq()
669 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_startup_port_v2()
673 const struct mtk_pcie_soc *soc = port->pcie->soc; in mtk_pcie_startup_port_v2()
677 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); in mtk_pcie_startup_port_v2()
679 mem = entry->res; in mtk_pcie_startup_port_v2()
681 return -EINVAL; in mtk_pcie_startup_port_v2()
684 if (pcie->base) { in mtk_pcie_startup_port_v2()
685 val = readl(pcie->base + PCIE_SYS_CFG_V2); in mtk_pcie_startup_port_v2()
686 val |= PCIE_CSR_LTSSM_EN(port->slot) | in mtk_pcie_startup_port_v2()
687 PCIE_CSR_ASPM_L1_EN(port->slot); in mtk_pcie_startup_port_v2()
688 writel(val, pcie->base + PCIE_SYS_CFG_V2); in mtk_pcie_startup_port_v2()
689 } else if (pcie->cfg) { in mtk_pcie_startup_port_v2()
690 val = PCIE_CSR_LTSSM_EN(port->slot) | in mtk_pcie_startup_port_v2()
691 PCIE_CSR_ASPM_L1_EN(port->slot); in mtk_pcie_startup_port_v2()
692 regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); in mtk_pcie_startup_port_v2()
696 writel(0, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
703 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
705 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ in mtk_pcie_startup_port_v2()
706 val = readl(port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
709 writel(val, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
712 if (soc->need_fix_class_id) { in mtk_pcie_startup_port_v2()
714 writew(val, port->base + PCIE_CONF_VEND_ID); in mtk_pcie_startup_port_v2()
717 writew(val, port->base + PCIE_CONF_CLASS_ID); in mtk_pcie_startup_port_v2()
720 if (soc->need_fix_device_id) in mtk_pcie_startup_port_v2()
721 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); in mtk_pcie_startup_port_v2()
724 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, in mtk_pcie_startup_port_v2()
728 return -ETIMEDOUT; in mtk_pcie_startup_port_v2()
731 val = readl(port->base + PCIE_INT_MASK); in mtk_pcie_startup_port_v2()
733 writel(val, port->base + PCIE_INT_MASK); in mtk_pcie_startup_port_v2()
739 val = lower_32_bits(mem->start) | in mtk_pcie_startup_port_v2()
741 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); in mtk_pcie_startup_port_v2()
743 val = upper_32_bits(mem->start); in mtk_pcie_startup_port_v2()
744 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); in mtk_pcie_startup_port_v2()
748 writel(val, port->base + PCIE_AXI_WINDOW0); in mtk_pcie_startup_port_v2()
756 struct mtk_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus()
759 bus->number), pcie->base + PCIE_CFG_ADDR); in mtk_pcie_map_bus()
761 return pcie->base + PCIE_CFG_DATA + (where & 3); in mtk_pcie_map_bus()
772 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_startup_port()
773 u32 func = PCI_FUNC(port->slot); in mtk_pcie_startup_port()
774 u32 slot = PCI_SLOT(port->slot << 3); in mtk_pcie_startup_port()
779 val = readl(pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
780 val |= PCIE_PORT_PERST(port->slot); in mtk_pcie_startup_port()
781 writel(val, pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
783 /* de-assert port PERST_N */ in mtk_pcie_startup_port()
784 val = readl(pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
785 val &= ~PCIE_PORT_PERST(port->slot); in mtk_pcie_startup_port()
786 writel(val, pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
789 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, in mtk_pcie_startup_port()
793 return -ETIMEDOUT; in mtk_pcie_startup_port()
796 val = readl(pcie->base + PCIE_INT_ENABLE); in mtk_pcie_startup_port()
797 val |= PCIE_PORT_INT_EN(port->slot); in mtk_pcie_startup_port()
798 writel(val, pcie->base + PCIE_INT_ENABLE); in mtk_pcie_startup_port()
802 port->base + PCIE_BAR0_SETUP); in mtk_pcie_startup_port()
805 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); in mtk_pcie_startup_port()
809 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
810 val = readl(pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
814 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
815 writel(val, pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
819 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
820 val = readl(pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
824 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
825 writel(val, pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
832 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_enable_port()
833 struct device *dev = pcie->dev; in mtk_pcie_enable_port()
836 err = clk_prepare_enable(port->sys_ck); in mtk_pcie_enable_port()
838 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); in mtk_pcie_enable_port()
842 err = clk_prepare_enable(port->ahb_ck); in mtk_pcie_enable_port()
844 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); in mtk_pcie_enable_port()
848 err = clk_prepare_enable(port->aux_ck); in mtk_pcie_enable_port()
850 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); in mtk_pcie_enable_port()
854 err = clk_prepare_enable(port->axi_ck); in mtk_pcie_enable_port()
856 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); in mtk_pcie_enable_port()
860 err = clk_prepare_enable(port->obff_ck); in mtk_pcie_enable_port()
862 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); in mtk_pcie_enable_port()
866 err = clk_prepare_enable(port->pipe_ck); in mtk_pcie_enable_port()
868 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); in mtk_pcie_enable_port()
872 reset_control_assert(port->reset); in mtk_pcie_enable_port()
873 reset_control_deassert(port->reset); in mtk_pcie_enable_port()
875 err = phy_init(port->phy); in mtk_pcie_enable_port()
877 dev_err(dev, "failed to initialize port%d phy\n", port->slot); in mtk_pcie_enable_port()
881 err = phy_power_on(port->phy); in mtk_pcie_enable_port()
883 dev_err(dev, "failed to power on port%d phy\n", port->slot); in mtk_pcie_enable_port()
887 if (!pcie->soc->startup(port)) in mtk_pcie_enable_port()
890 dev_info(dev, "Port%d link down\n", port->slot); in mtk_pcie_enable_port()
892 phy_power_off(port->phy); in mtk_pcie_enable_port()
894 phy_exit(port->phy); in mtk_pcie_enable_port()
896 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_enable_port()
898 clk_disable_unprepare(port->obff_ck); in mtk_pcie_enable_port()
900 clk_disable_unprepare(port->axi_ck); in mtk_pcie_enable_port()
902 clk_disable_unprepare(port->aux_ck); in mtk_pcie_enable_port()
904 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_enable_port()
906 clk_disable_unprepare(port->sys_ck); in mtk_pcie_enable_port()
916 struct device *dev = pcie->dev; in mtk_pcie_parse_port()
923 return -ENOMEM; in mtk_pcie_parse_port()
926 port->base = devm_platform_ioremap_resource_byname(pdev, name); in mtk_pcie_parse_port()
927 if (IS_ERR(port->base)) { in mtk_pcie_parse_port()
929 return PTR_ERR(port->base); in mtk_pcie_parse_port()
933 port->sys_ck = devm_clk_get(dev, name); in mtk_pcie_parse_port()
934 if (IS_ERR(port->sys_ck)) { in mtk_pcie_parse_port()
936 return PTR_ERR(port->sys_ck); in mtk_pcie_parse_port()
941 port->ahb_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
942 if (IS_ERR(port->ahb_ck)) in mtk_pcie_parse_port()
943 return PTR_ERR(port->ahb_ck); in mtk_pcie_parse_port()
946 port->axi_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
947 if (IS_ERR(port->axi_ck)) in mtk_pcie_parse_port()
948 return PTR_ERR(port->axi_ck); in mtk_pcie_parse_port()
951 port->aux_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
952 if (IS_ERR(port->aux_ck)) in mtk_pcie_parse_port()
953 return PTR_ERR(port->aux_ck); in mtk_pcie_parse_port()
956 port->obff_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
957 if (IS_ERR(port->obff_ck)) in mtk_pcie_parse_port()
958 return PTR_ERR(port->obff_ck); in mtk_pcie_parse_port()
961 port->pipe_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
962 if (IS_ERR(port->pipe_ck)) in mtk_pcie_parse_port()
963 return PTR_ERR(port->pipe_ck); in mtk_pcie_parse_port()
965 snprintf(name, sizeof(name), "pcie-rst%d", slot); in mtk_pcie_parse_port()
966 port->reset = devm_reset_control_get_optional_exclusive(dev, name); in mtk_pcie_parse_port()
967 if (PTR_ERR(port->reset) == -EPROBE_DEFER) in mtk_pcie_parse_port()
968 return PTR_ERR(port->reset); in mtk_pcie_parse_port()
971 snprintf(name, sizeof(name), "pcie-phy%d", slot); in mtk_pcie_parse_port()
972 port->phy = devm_phy_optional_get(dev, name); in mtk_pcie_parse_port()
973 if (IS_ERR(port->phy)) in mtk_pcie_parse_port()
974 return PTR_ERR(port->phy); in mtk_pcie_parse_port()
976 port->slot = slot; in mtk_pcie_parse_port()
977 port->pcie = pcie; in mtk_pcie_parse_port()
979 if (pcie->soc->setup_irq) { in mtk_pcie_parse_port()
980 err = pcie->soc->setup_irq(port, node); in mtk_pcie_parse_port()
985 INIT_LIST_HEAD(&port->list); in mtk_pcie_parse_port()
986 list_add_tail(&port->list, &pcie->ports); in mtk_pcie_parse_port()
993 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerup()
1002 pcie->base = devm_ioremap_resource(dev, regs); in mtk_pcie_subsys_powerup()
1003 if (IS_ERR(pcie->base)) in mtk_pcie_subsys_powerup()
1004 return PTR_ERR(pcie->base); in mtk_pcie_subsys_powerup()
1008 "mediatek,generic-pciecfg"); in mtk_pcie_subsys_powerup()
1010 pcie->cfg = syscon_node_to_regmap(cfg_node); in mtk_pcie_subsys_powerup()
1011 if (IS_ERR(pcie->cfg)) in mtk_pcie_subsys_powerup()
1012 return PTR_ERR(pcie->cfg); in mtk_pcie_subsys_powerup()
1015 pcie->free_ck = devm_clk_get(dev, "free_ck"); in mtk_pcie_subsys_powerup()
1016 if (IS_ERR(pcie->free_ck)) { in mtk_pcie_subsys_powerup()
1017 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) in mtk_pcie_subsys_powerup()
1018 return -EPROBE_DEFER; in mtk_pcie_subsys_powerup()
1020 pcie->free_ck = NULL; in mtk_pcie_subsys_powerup()
1027 err = clk_prepare_enable(pcie->free_ck); in mtk_pcie_subsys_powerup()
1044 struct device *dev = pcie->dev; in mtk_pcie_setup()
1045 struct device_node *node = dev->of_node, *child; in mtk_pcie_setup()
1049 slot = of_get_pci_domain_nr(dev->of_node); in mtk_pcie_setup()
1075 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in mtk_pcie_setup()
1079 if (list_empty(&pcie->ports)) in mtk_pcie_setup()
1090 struct device *dev = &pdev->dev; in mtk_pcie_probe()
1097 return -ENOMEM; in mtk_pcie_probe()
1101 pcie->dev = dev; in mtk_pcie_probe()
1102 pcie->soc = of_device_get_match_data(dev); in mtk_pcie_probe()
1104 INIT_LIST_HEAD(&pcie->ports); in mtk_pcie_probe()
1110 host->ops = pcie->soc->ops; in mtk_pcie_probe()
1111 host->sysdata = pcie; in mtk_pcie_probe()
1112 host->msi_domain = pcie->soc->no_msi; in mtk_pcie_probe()
1121 if (!list_empty(&pcie->ports)) in mtk_pcie_probe()
1131 struct list_head *windows = &host->windows; in mtk_pcie_free_resources()
1141 pci_stop_root_bus(host->bus); in mtk_pcie_remove()
1142 pci_remove_root_bus(host->bus); in mtk_pcie_remove()
1157 if (list_empty(&pcie->ports)) in mtk_pcie_suspend_noirq()
1160 list_for_each_entry(port, &pcie->ports, list) { in mtk_pcie_suspend_noirq()
1161 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_suspend_noirq()
1162 clk_disable_unprepare(port->obff_ck); in mtk_pcie_suspend_noirq()
1163 clk_disable_unprepare(port->axi_ck); in mtk_pcie_suspend_noirq()
1164 clk_disable_unprepare(port->aux_ck); in mtk_pcie_suspend_noirq()
1165 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_suspend_noirq()
1166 clk_disable_unprepare(port->sys_ck); in mtk_pcie_suspend_noirq()
1167 phy_power_off(port->phy); in mtk_pcie_suspend_noirq()
1168 phy_exit(port->phy); in mtk_pcie_suspend_noirq()
1171 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_suspend_noirq()
1181 if (list_empty(&pcie->ports)) in mtk_pcie_resume_noirq()
1184 clk_prepare_enable(pcie->free_ck); in mtk_pcie_resume_noirq()
1186 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in mtk_pcie_resume_noirq()
1190 if (list_empty(&pcie->ports)) in mtk_pcie_resume_noirq()
1191 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_resume_noirq()
1230 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1231 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1232 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1233 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1234 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1243 .name = "mtk-pcie",