Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
17 #include <linux/irqchip/arm-gic-v3.h>
25 #include "pcie-iproc.h"
63 /* derive the enum index of the outbound/inbound mapping registers */
67 * Maximum number of outbound mapping window sizes that can be supported by any
92 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
94 * @window_sizes: list of supported outbound mapping window sizes in MB
95 * @nr_sizes: number of supported outbound mapping window sizes
139 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
151 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
160 * @imap_addr_offset: register offset between the upper and lower 32-bit
272 /* outbound address mapping */
401 struct iproc_pcie *pcie = bus->sysdata; in iproc_data()
413 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
424 return readl(pcie->base + offset); in iproc_pcie_read_reg()
435 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
441 * (typically seen during enumeration with multi-function devices) from
450 if (bus->number && pcie->has_apb_err_disable) { in iproc_pcie_apb_err_disable()
478 return (pcie->base + offset); in iproc_pcie_map_ep_cfg_reg()
500 * Note that a non-Vendor ID config register may have a value of in iproc_pcie_cfg_retry()
506 while (data == CFG_RETRY_STATUS && timeout--) { in iproc_pcie_cfg_retry()
540 pcie->fix_paxc_cap = true; in iproc_pcie_fix_cap()
544 if (pcie->fix_paxc_cap) { in iproc_pcie_fix_cap()
552 if (pcie->fix_paxc_cap) { in iproc_pcie_fix_cap()
573 unsigned int busno = bus->number; in iproc_pcie_config_read()
596 *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pcie_config_read()
611 if (pcie->rej_unconfig_pf && in iproc_pcie_config_read()
641 return (pcie->base + offset); in iproc_pcie_map_cfg_bus()
651 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn, in iproc_pcie_bus_map_cfg_bus()
670 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); in iproc_pci_raw_config_read32()
691 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8)); in iproc_pci_raw_config_write32()
706 if (pcie->iproc_cfg_read) in iproc_pcie_config_read32()
742 if (pcie->ep_is_internal) in iproc_pcie_perst_ctrl()
770 struct device *dev = pcie->dev; in iproc_pcie_check_link()
778 if (pcie->ep_is_internal) in iproc_pcie_check_link()
784 return -ENODEV; in iproc_pcie_check_link()
791 return -EFAULT; in iproc_pcie_check_link()
838 return link_is_active ? 0 : -ENODEV; in iproc_pcie_check_link()
859 struct device *dev = pcie->dev; in iproc_pcie_ob_write()
872 return -EINVAL; in iproc_pcie_ob_write()
875 * Program the OARR registers. The upper 32-bit OARR register is in iproc_pcie_ob_write()
876 * always right after the lower 32-bit OARR register. in iproc_pcie_ob_write()
879 OARR_VALID, pcie->base + oarr_offset); in iproc_pcie_ob_write()
880 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4); in iproc_pcie_ob_write()
883 writel(lower_32_bits(pci_addr), pcie->base + omap_offset); in iproc_pcie_ob_write()
884 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4); in iproc_pcie_ob_write()
889 readl(pcie->base + oarr_offset), in iproc_pcie_ob_write()
890 readl(pcie->base + oarr_offset + 4)); in iproc_pcie_ob_write()
892 readl(pcie->base + omap_offset), in iproc_pcie_ob_write()
893 readl(pcie->base + omap_offset + 4)); in iproc_pcie_ob_write()
899 * Some iProc SoCs require the SW to configure the outbound address mapping
901 * Outbound address translation:
903 * iproc_pcie_address = axi_address - axi_offset
907 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
912 struct iproc_pcie_ob *ob = &pcie->ob; in iproc_pcie_setup_ob()
913 struct device *dev = pcie->dev; in iproc_pcie_setup_ob()
914 int ret = -EINVAL, window_idx, size_idx; in iproc_pcie_setup_ob()
916 if (axi_addr < ob->axi_offset) { in iproc_pcie_setup_ob()
918 &axi_addr, &ob->axi_offset); in iproc_pcie_setup_ob()
919 return -EINVAL; in iproc_pcie_setup_ob()
926 axi_addr -= ob->axi_offset; in iproc_pcie_setup_ob()
929 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) { in iproc_pcie_setup_ob()
931 &pcie->ob_map[window_idx]; in iproc_pcie_setup_ob()
934 * If current outbound window is already in use, move on to the in iproc_pcie_setup_ob()
945 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0; in iproc_pcie_setup_ob()
946 size_idx--) { in iproc_pcie_setup_ob()
948 ob_map->window_sizes[size_idx] * SZ_1M; in iproc_pcie_setup_ob()
975 return -EINVAL; in iproc_pcie_setup_ob()
987 size -= window_size; in iproc_pcie_setup_ob()
1003 dev_err(dev, "unable to configure outbound mapping\n"); in iproc_pcie_setup_ob()
1006 &axi_addr, &ob->axi_offset, &pci_addr, &size); in iproc_pcie_setup_ob()
1014 struct device *dev = pcie->dev; in iproc_pcie_map_ranges()
1019 struct resource *res = window->res; in iproc_pcie_map_ranges()
1027 ret = iproc_pcie_setup_ob(pcie, res->start, in iproc_pcie_map_ranges()
1028 res->start - window->offset, in iproc_pcie_map_ranges()
1035 return -EINVAL; in iproc_pcie_map_ranges()
1045 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; in iproc_pcie_ib_is_in_use()
1050 return !!(val & (BIT(ib_map->nr_sizes) - 1)); in iproc_pcie_ib_is_in_use()
1056 return !!(ib_map->type == type); in iproc_pcie_ib_check_type()
1063 struct device *dev = pcie->dev; in iproc_pcie_ib_write()
1064 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx]; in iproc_pcie_ib_write()
1075 return -EINVAL; in iproc_pcie_ib_write()
1081 * Program the IARR registers. The upper 32-bit IARR register is in iproc_pcie_ib_write()
1082 * always right after the lower 32-bit IARR register. in iproc_pcie_ib_write()
1085 pcie->base + iarr_offset); in iproc_pcie_ib_write()
1086 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4); in iproc_pcie_ib_write()
1089 readl(pcie->base + iarr_offset), in iproc_pcie_ib_write()
1090 readl(pcie->base + iarr_offset + 4)); in iproc_pcie_ib_write()
1098 val = readl(pcie->base + imap_offset); in iproc_pcie_ib_write()
1100 writel(val, pcie->base + imap_offset); in iproc_pcie_ib_write()
1102 pcie->base + imap_offset + ib_map->imap_addr_offset); in iproc_pcie_ib_write()
1105 window_idx, readl(pcie->base + imap_offset), in iproc_pcie_ib_write()
1106 readl(pcie->base + imap_offset + in iproc_pcie_ib_write()
1107 ib_map->imap_addr_offset)); in iproc_pcie_ib_write()
1109 imap_offset += ib_map->imap_window_offset; in iproc_pcie_ib_write()
1120 struct device *dev = pcie->dev; in iproc_pcie_setup_ib()
1121 struct iproc_pcie_ib *ib = &pcie->ib; in iproc_pcie_setup_ib()
1124 u64 axi_addr = entry->res->start; in iproc_pcie_setup_ib()
1125 u64 pci_addr = entry->res->start - entry->offset; in iproc_pcie_setup_ib()
1126 resource_size_t size = resource_size(entry->res); in iproc_pcie_setup_ib()
1128 /* iterate through all IARR mapping regions */ in iproc_pcie_setup_ib()
1129 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) { in iproc_pcie_setup_ib()
1131 &pcie->ib_map[region_idx]; in iproc_pcie_setup_ib()
1142 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) { in iproc_pcie_setup_ib()
1144 ib_map->region_sizes[size_idx] * ib_map->size_unit; in iproc_pcie_setup_ib()
1154 return -EINVAL; in iproc_pcie_setup_ib()
1159 ib_map->nr_windows, axi_addr, in iproc_pcie_setup_ib()
1168 ret = -EINVAL; in iproc_pcie_setup_ib()
1184 resource_list_for_each_entry(entry, &host->dma_ranges) { in iproc_pcie_map_dma_ranges()
1196 struct iproc_pcie_ib *ib = &pcie->ib; in iproc_pcie_invalidate_mapping()
1197 struct iproc_pcie_ob *ob = &pcie->ob; in iproc_pcie_invalidate_mapping()
1200 if (pcie->ep_is_internal) in iproc_pcie_invalidate_mapping()
1203 if (pcie->need_ob_cfg) { in iproc_pcie_invalidate_mapping()
1204 /* iterate through all OARR mapping regions */ in iproc_pcie_invalidate_mapping()
1205 for (idx = ob->nr_windows - 1; idx >= 0; idx--) { in iproc_pcie_invalidate_mapping()
1211 if (pcie->need_ib_cfg) { in iproc_pcie_invalidate_mapping()
1212 /* iterate through all IARR mapping regions */ in iproc_pcie_invalidate_mapping()
1213 for (idx = 0; idx < ib->nr_regions; idx++) { in iproc_pcie_invalidate_mapping()
1224 struct device *dev = pcie->dev; in iproce_pcie_get_msi()
1229 * Check if 'msi-map' points to ARM GICv3 ITS, which is the only in iproce_pcie_get_msi()
1232 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) { in iproce_pcie_get_msi()
1234 return -ENODEV; in iproce_pcie_get_msi()
1256 msi_addr &= ~(SZ_32K - 1); in iproc_pcie_paxb_v2_msi_steer()
1257 entry.res->start = msi_addr; in iproc_pcie_paxb_v2_msi_steer()
1258 entry.res->end = msi_addr + SZ_32K - 1; in iproc_pcie_paxb_v2_msi_steer()
1272 * treated as non-MSI transfers in iproc_pcie_paxc_v2_msi_steer()
1283 * based SoCs, all I/O register bases are well below the 32-bit in iproc_pcie_paxc_v2_msi_steer()
1316 struct device *dev = pcie->dev; in iproc_pcie_msi_steer()
1326 switch (pcie->type) { in iproc_pcie_msi_steer()
1336 return -EINVAL; in iproc_pcie_msi_steer()
1348 * Either the "msi-parent" or the "msi-map" phandle needs to exist in iproc_pcie_msi_enable()
1352 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0); in iproc_pcie_msi_enable()
1358 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len); in iproc_pcie_msi_enable()
1360 return -ENODEV; in iproc_pcie_msi_enable()
1365 return -ENODEV; in iproc_pcie_msi_enable()
1373 if (pcie->need_msi_steer) { in iproc_pcie_msi_enable()
1397 struct device *dev = pcie->dev; in iproc_pcie_rev_init()
1401 switch (pcie->type) { in iproc_pcie_rev_init()
1407 pcie->has_apb_err_disable = true; in iproc_pcie_rev_init()
1408 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
1409 pcie->ob_map = paxb_ob_map; in iproc_pcie_rev_init()
1410 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map); in iproc_pcie_rev_init()
1415 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1416 pcie->has_apb_err_disable = true; in iproc_pcie_rev_init()
1417 if (pcie->need_ob_cfg) { in iproc_pcie_rev_init()
1418 pcie->ob_map = paxb_v2_ob_map; in iproc_pcie_rev_init()
1419 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map); in iproc_pcie_rev_init()
1421 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map); in iproc_pcie_rev_init()
1422 pcie->ib_map = paxb_v2_ib_map; in iproc_pcie_rev_init()
1423 pcie->need_msi_steer = true; in iproc_pcie_rev_init()
1429 pcie->ep_is_internal = true; in iproc_pcie_rev_init()
1430 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1431 pcie->rej_unconfig_pf = true; in iproc_pcie_rev_init()
1435 pcie->ep_is_internal = true; in iproc_pcie_rev_init()
1436 pcie->iproc_cfg_read = true; in iproc_pcie_rev_init()
1437 pcie->rej_unconfig_pf = true; in iproc_pcie_rev_init()
1438 pcie->need_msi_steer = true; in iproc_pcie_rev_init()
1442 return -EINVAL; in iproc_pcie_rev_init()
1445 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, in iproc_pcie_rev_init()
1446 sizeof(*pcie->reg_offsets), in iproc_pcie_rev_init()
1448 if (!pcie->reg_offsets) in iproc_pcie_rev_init()
1449 return -ENOMEM; in iproc_pcie_rev_init()
1452 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1455 pcie->reg_offsets[reg_idx] = regs[reg_idx] ? in iproc_pcie_rev_init()
1468 dev = pcie->dev; in iproc_pcie_setup()
1476 ret = phy_init(pcie->phy); in iproc_pcie_setup()
1482 ret = phy_power_on(pcie->phy); in iproc_pcie_setup()
1493 if (pcie->need_ob_cfg) { in iproc_pcie_setup()
1501 if (pcie->need_ib_cfg) { in iproc_pcie_setup()
1503 if (ret && ret != -ENOENT) in iproc_pcie_setup()
1519 host->ops = &iproc_pcie_ops; in iproc_pcie_setup()
1520 host->sysdata = pcie; in iproc_pcie_setup()
1521 host->map_irq = pcie->map_irq; in iproc_pcie_setup()
1529 for_each_pci_bridge(pdev, host->bus) { in iproc_pcie_setup()
1537 phy_power_off(pcie->phy); in iproc_pcie_setup()
1539 phy_exit(pcie->phy); in iproc_pcie_setup()
1548 pci_stop_root_bus(host->bus); in iproc_pcie_remove()
1549 pci_remove_root_bus(host->bus); in iproc_pcie_remove()
1553 phy_power_off(pcie->phy); in iproc_pcie_remove()
1554 phy_exit(pcie->phy); in iproc_pcie_remove()
1566 struct iproc_pcie *pcie = iproc_data(pdev->bus); in quirk_paxc_disable_msi_parsing()
1568 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in quirk_paxc_disable_msi_parsing()
1585 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in quirk_paxc_bridge()
1586 pdev->class = PCI_CLASS_BRIDGE_PCI << 8; in quirk_paxc_bridge()
1592 * so that the MPS can be set to the real max value. in quirk_paxc_bridge()
1594 pdev->pcie_mpss = 2; in quirk_paxc_bridge()