24 #define RP_TX_REG0			0x2000
25 #define RP_TX_REG1			0x2004
26 #define RP_TX_CNTRL			0x2008
27 #define RP_TX_EOP			0x2
28 #define RP_TX_SOP			0x1
29 #define RP_RXCPL_STATUS			0x2010
30 #define RP_RXCPL_EOP			0x2
31 #define RP_RXCPL_SOP			0x1
32 #define RP_RXCPL_REG0			0x2014
33 #define RP_RXCPL_REG1			0x2018
34 #define P2A_INT_STATUS			0x3060
35 #define P2A_INT_STS_ALL			0xf
36 #define P2A_INT_ENABLE			0x3070
37 #define P2A_INT_ENA_ALL			0xf
38 #define RP_LTSSM			0x3c64
39 #define RP_LTSSM_MASK			0x1f
40 #define LTSSM_L0			0xf
42 #define S10_RP_TX_CNTRL			0x2004
43 #define S10_RP_RXCPL_REG		0x2008
44 #define S10_RP_RXCPL_STATUS		0x200C
50 /* TLP configuration type 0 and 1 */
51 #define TLP_FMTTYPE_CFGRD0		0x04	/* Configuration Read Type 0 */
52 #define TLP_FMTTYPE_CFGWR0		0x44	/* Configuration Write Type 0 */
53 #define TLP_FMTTYPE_CFGRD1		0x05	/* Configuration Read Type 1 */
54 #define TLP_FMTTYPE_CFGWR1		0x45	/* Configuration Write Type 1 */
55 #define TLP_PAYLOAD_SIZE		0x01
56 #define TLP_READ_TAG			0x1d
57 #define TLP_WRITE_TAG			0x10
58 #define RP_DEVFN			0
68 #define TLP_BYTE_COUNT(s)		(((s) >> 0) & 0xfff)
77 #define S10_TLP_FMTTYPE_CFGRD0		0x05
78 #define S10_TLP_FMTTYPE_CFGRD1		0x04
79 #define S10_TLP_FMTTYPE_CFGWR0		0x45
80 #define S10_TLP_FMTTYPE_CFGWR1		0x44
83 	ALTERA_PCIE_V1 = 0,
162 	if (pci_is_root_bus(bus) && (devfn == 0) &&  in altera_pcie_hide_rc_bar()
193 	if (bus->number == pcie->root_bus_nr && dev > 0)  in altera_pcie_valid_device()
211 	for (i = 0; i < TLP_LOOP; i++) {  in tlp_read_packet()
246 	for (count = 0; count < TLP_LOOP; count++) {  in s10_tlp_read_packet()
250 			dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);  in s10_tlp_read_packet()
290 	tlp_rp_regdata.reg0 = headers[0];  in tlp_write_packet()
297 		tlp_rp_regdata.reg1 = 0;  in tlp_write_packet()
298 		tlp_rp_regdata.ctrl = 0;  in tlp_write_packet()
302 		tlp_rp_regdata.reg1 = 0;  in tlp_write_packet()
315 	s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);  in s10_tlp_write_packet()
316 	s10_tlp_write_tx(pcie, headers[1], 0);  in s10_tlp_write_packet()
317 	s10_tlp_write_tx(pcie, headers[2], 0);  in s10_tlp_write_packet()
334 	headers[0] = TLP_CFG_DW0(pcie, cfg);  in get_tlp_header()
347 	pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);  in tlp_cfg_dword_read()
362 	if ((where & 0x7) == 0)  in tlp_cfg_dword_write()
425 		pcie->root_bus_nr = value & 0xff;  in s10_rp_write_cfg()
450 		byte_en = 0xf;  in _altera_pcie_cfg_read()
461 		*value = (data >> (8 * (where & 0x3))) & 0xff;  in _altera_pcie_cfg_read()
464 		*value = (data >> (8 * (where & 0x2))) & 0xffff;  in _altera_pcie_cfg_read()
488 		data32 = (value & 0xff) << shift;  in _altera_pcie_cfg_write()
492 		data32 = (value & 0xffff) << shift;  in _altera_pcie_cfg_write()
497 		byte_en = 0xf;  in _altera_pcie_cfg_write()
514 		*value = 0xffffffff;  in altera_pcie_cfg_read()
634 	return 0;  in altera_pcie_intx_map()
656 		& P2A_INT_STS_ALL) != 0) {  in altera_pcie_isr()
683 	return 0;  in altera_pcie_init_irq_domain()
709 	pcie->irq = platform_get_irq(pdev, 0);  in altera_pcie_parse_dt()
710 	if (pcie->irq < 0)  in altera_pcie_parse_dt()
714 	return 0;  in altera_pcie_parse_dt()
738 	.cap_offset = 0x80,
749 	.cap_offset = 0x70,
820 	return 0;  in altera_pcie_remove()