255 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)  in advk_readl()  function
262 	return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8);  in advk_read16()
269 	val = advk_readl(pcie, CFG_REG);  in advk_pcie_link_up()
315 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);  in advk_pcie_issue_perst()
332 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);  in advk_pcie_train_at_gen()
346 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);  in advk_pcie_train_at_gen()
354 	reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);  in advk_pcie_train_at_gen()
455 	reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);  in advk_pcie_setup_hw()
460 	reg = advk_readl(pcie, CTRL_CONFIG_REG);  in advk_pcie_setup_hw()
466 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);  in advk_pcie_setup_hw()
488 	reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);  in advk_pcie_setup_hw()
502 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);  in advk_pcie_setup_hw()
508 	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);  in advk_pcie_setup_hw()
541 	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);  in advk_pcie_setup_hw()
558 	reg = advk_readl(pcie, PIO_CTRL);  in advk_pcie_setup_hw()
585 	reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);  in advk_pcie_setup_hw()
599 	reg = advk_readl(pcie, PIO_STAT);  in advk_pcie_check_pio_status()
626 			*val = advk_readl(pcie, PIO_RD_DATA);  in advk_pcie_check_pio_status()
686 		str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));  in advk_pcie_check_pio_status()
699 		start = advk_readl(pcie, PIO_START);  in advk_pcie_wait_pio()
700 		isr = advk_readl(pcie, PIO_ISR);  in advk_pcie_wait_pio()
724 		u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);  in advk_pci_bridge_emul_pcie_conf_read()
731 		u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);  in advk_pci_bridge_emul_pcie_conf_read()
732 		u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);  in advk_pci_bridge_emul_pcie_conf_read()
739 		u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &  in advk_pci_bridge_emul_pcie_conf_read()
751 		*value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);  in advk_pci_bridge_emul_pcie_conf_read()
778 		u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &  in advk_pci_bridge_emul_pcie_conf_write()
811 		cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);  in advk_sw_pci_bridge_init()
813 		cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);  in advk_sw_pci_bridge_init()
815 		cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);  in advk_sw_pci_bridge_init()
880 	if (advk_readl(pcie, PIO_START)) {  in advk_pcie_pio_is_running()
928 	reg = advk_readl(pcie, PIO_CTRL);  in advk_pcie_rd_conf()
1000 	reg = advk_readl(pcie, PIO_CTRL);  in advk_pcie_wr_conf()
1112 	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);  in advk_pcie_irq_mask()
1126 	mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);  in advk_pcie_irq_unmask()
1258 	msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);  in advk_pcie_handle_msi()
1259 	msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);  in advk_pcie_handle_msi()
1267 		msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;  in advk_pcie_handle_msi()
1281 	isr0_val = advk_readl(pcie, PCIE_ISR0_REG);  in advk_pcie_handle_int()
1282 	isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);  in advk_pcie_handle_int()
1285 	isr1_val = advk_readl(pcie, PCIE_ISR1_REG);  in advk_pcie_handle_int()
1286 	isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);  in advk_pcie_handle_int()
1316 	status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);  in advk_pcie_irq_handler()