Lines Matching +full:de +full:- +full:asserting
1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/pci-ecam.h>
29 #include "../pci-bridge-emul.h"
137 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
252 writel(val, pcie->base + reg); in advk_writel()
257 return readl(pcie->base + reg); in advk_readl()
286 return -ETIMEDOUT; in advk_pcie_wait_for_link()
304 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
310 * for at least 100ms after de-asserting PERST# signal is needed before in advk_pcie_issue_perst()
312 * prior de-asserting PERST# signal to fulfill that PCI Express spec in advk_pcie_issue_perst()
320 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
321 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
323 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
370 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
371 int neg_gen = -1, gen; in advk_pcie_train_link()
375 * during link training when they are in some non-initial state. in advk_pcie_train_link()
390 * 'max-link-speed'. If this fails, iteratively train at lower gen. in advk_pcie_train_link()
392 for (gen = pcie->link_gen; gen > 0; --gen) { in advk_pcie_train_link()
474 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround in advk_pcie_setup_hw()
563 * Configure PCIe address windows for non-memory or in advk_pcie_setup_hw()
564 * non-transparent access as by default PCIe uses in advk_pcie_setup_hw()
567 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
569 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
570 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
573 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
594 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
641 * read-data value of 0001h for the Vendor ID field and in advk_pcie_check_pio_status()
653 * must re-issue the Configuration Request as a new Request. in advk_pcie_check_pio_status()
656 * the Root Complex must re-issue the Configuration Request as in advk_pcie_check_pio_status()
664 * To simplify implementation do not re-issue the Configuration in advk_pcie_check_pio_status()
681 str_posted = "Non-posted"; in advk_pcie_check_pio_status()
688 return -EFAULT; in advk_pcie_check_pio_status()
693 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
707 return -ETIMEDOUT; in advk_pcie_wait_pio()
715 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read()
763 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write()
802 * Initialize the configuration space of the PCI-to-PCI bridge
807 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
810 bridge->conf.vendor = in advk_sw_pci_bridge_init()
812 bridge->conf.device = in advk_sw_pci_bridge_init()
814 bridge->conf.class_revision = in advk_sw_pci_bridge_init()
818 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
819 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
822 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
823 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
826 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; in advk_sw_pci_bridge_init()
828 bridge->has_pcie = true; in advk_sw_pci_bridge_init()
829 bridge->data = pcie; in advk_sw_pci_bridge_init()
830 bridge->ops = &advk_pci_bridge_emul_ops; in advk_sw_pci_bridge_init()
838 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); in advk_sw_pci_bridge_init()
850 * If the link goes down after we check for link-up, nothing bad in advk_pcie_valid_device()
861 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
867 * SError Interrupt on CPU0, code 0xbf000002 -- SError in advk_pcie_pio_is_running()
868 * Kernel panic - not syncing: Asynchronous SError Interrupt in advk_pcie_pio_is_running()
877 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: in advk_pcie_pio_is_running()
878 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 in advk_pcie_pio_is_running()
891 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf()
902 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
911 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
930 if (pci_is_root_bus(bus->parent)) in advk_pcie_rd_conf()
937 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); in advk_pcie_rd_conf()
980 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf()
990 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1002 if (pci_is_root_bus(bus->parent)) in advk_pcie_wr_conf()
1009 reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4); in advk_pcie_wr_conf()
1016 data_strobe = GENMASK(size - 1, 0) << offset; in advk_pcie_wr_conf()
1048 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); in advk_msi_irq_compose_msi_msg()
1050 msg->address_lo = lower_32_bits(msi_msg); in advk_msi_irq_compose_msi_msg()
1051 msg->address_hi = upper_32_bits(msi_msg); in advk_msi_irq_compose_msi_msg()
1052 msg->data = data->irq; in advk_msi_irq_compose_msi_msg()
1058 return -EINVAL; in advk_msi_set_affinity()
1065 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc()
1068 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1069 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1072 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1073 return -ENOSPC; in advk_msi_irq_domain_alloc()
1076 bitmap_set(pcie->msi_used, hwirq, nr_irqs); in advk_msi_irq_domain_alloc()
1077 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1081 &pcie->msi_bottom_irq_chip, in advk_msi_irq_domain_alloc()
1082 domain->host_data, handle_simple_irq, in advk_msi_irq_domain_alloc()
1092 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free()
1094 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1095 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); in advk_msi_irq_domain_free()
1096 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1106 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask()
1111 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1115 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1120 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask()
1125 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1129 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1135 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map()
1139 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1153 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1154 struct device_node *node = dev->of_node; in advk_pcie_init_msi_irq_domain()
1159 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1161 bottom_ic = &pcie->msi_bottom_irq_chip; in advk_pcie_init_msi_irq_domain()
1163 bottom_ic->name = "MSI"; in advk_pcie_init_msi_irq_domain()
1164 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; in advk_pcie_init_msi_irq_domain()
1165 bottom_ic->irq_set_affinity = advk_msi_set_affinity; in advk_pcie_init_msi_irq_domain()
1167 msi_ic = &pcie->msi_irq_chip; in advk_pcie_init_msi_irq_domain()
1168 msi_ic->name = "advk-MSI"; in advk_pcie_init_msi_irq_domain()
1170 msi_di = &pcie->msi_domain_info; in advk_pcie_init_msi_irq_domain()
1171 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | in advk_pcie_init_msi_irq_domain()
1173 msi_di->chip = msi_ic; in advk_pcie_init_msi_irq_domain()
1175 msi_msg_phys = virt_to_phys(&pcie->msi_msg); in advk_pcie_init_msi_irq_domain()
1182 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1185 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1186 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1188 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1190 msi_di, pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1191 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1192 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1193 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1201 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1202 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1207 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1208 struct device_node *node = dev->of_node; in advk_pcie_init_irq_domain()
1213 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1218 return -ENODEV; in advk_pcie_init_irq_domain()
1221 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1223 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", in advk_pcie_init_irq_domain()
1225 if (!irq_chip->name) { in advk_pcie_init_irq_domain()
1226 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1230 irq_chip->irq_mask = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1231 irq_chip->irq_mask_ack = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1232 irq_chip->irq_unmask = advk_pcie_irq_unmask; in advk_pcie_init_irq_domain()
1234 pcie->irq_domain = in advk_pcie_init_irq_domain()
1237 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1239 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1250 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1307 generic_handle_domain_irq(pcie->irq_domain, i); in advk_pcie_handle_int()
1330 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1331 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1338 if (!pcie->phy) in advk_pcie_enable_phy()
1341 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1345 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1347 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1351 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1352 if (ret == -EOPNOTSUPP) { in advk_pcie_enable_phy()
1353 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); in advk_pcie_enable_phy()
1355 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1364 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1365 struct device_node *node = dev->of_node; in advk_pcie_setup_phy()
1368 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1369 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1370 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1373 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1374 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1375 pcie->phy = NULL; in advk_pcie_setup_phy()
1388 struct device *dev = &pdev->dev; in advk_pcie_probe()
1396 return -ENOMEM; in advk_pcie_probe()
1399 pcie->pdev = pdev; in advk_pcie_probe()
1402 resource_list_for_each_entry(entry, &bridge->windows) { in advk_pcie_probe()
1403 resource_size_t start = entry->res->start; in advk_pcie_probe()
1404 resource_size_t size = resource_size(entry->res); in advk_pcie_probe()
1405 unsigned long type = resource_type(entry->res); in advk_pcie_probe()
1424 entry->offset == 0) in advk_pcie_probe()
1428 * The n-th PCIe window is configured by tuple (match, remap, mask) in advk_pcie_probe()
1436 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1438 win_size = (1ULL << (fls64(size)-1)) | in advk_pcie_probe()
1445 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", in advk_pcie_probe()
1446 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1450 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1451 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1453 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1454 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1456 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1457 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1459 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1463 size -= win_size; in advk_pcie_probe()
1464 pcie->wins_count++; in advk_pcie_probe()
1468 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1469 "Invalid PCIe region [0x%llx-0x%llx]\n", in advk_pcie_probe()
1470 (unsigned long long)entry->res->start, in advk_pcie_probe()
1471 (unsigned long long)entry->res->end + 1); in advk_pcie_probe()
1472 return -EINVAL; in advk_pcie_probe()
1476 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1477 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1478 return PTR_ERR(pcie->base); in advk_pcie_probe()
1485 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", in advk_pcie_probe()
1492 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, in advk_pcie_probe()
1493 "reset-gpios", 0, in advk_pcie_probe()
1495 "pcie1-reset"); in advk_pcie_probe()
1496 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1498 if (ret == -ENOENT) { in advk_pcie_probe()
1499 pcie->reset_gpio = NULL; in advk_pcie_probe()
1501 if (ret != -EPROBE_DEFER) in advk_pcie_probe()
1502 dev_err(dev, "Failed to get reset-gpio: %i\n", in advk_pcie_probe()
1508 ret = of_pci_get_max_link_speed(dev->of_node); in advk_pcie_probe()
1510 pcie->link_gen = 3; in advk_pcie_probe()
1512 pcie->link_gen = ret; in advk_pcie_probe()
1539 bridge->sysdata = pcie; in advk_pcie_probe()
1540 bridge->ops = &advk_pcie_ops; in advk_pcie_probe()
1559 pci_stop_root_bus(bridge->bus); in advk_pcie_remove()
1560 pci_remove_root_bus(bridge->bus); in advk_pcie_remove()
1574 { .compatible = "marvell,armada-3700-pcie", },
1581 .name = "advk-pcie",