Lines Matching +full:aspm +full:- +full:no +full:- +full:l0s
1 // SPDX-License-Identifier: GPL-2.0+
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
304 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
309 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
324 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
326 * transitioning to Gen-2 speed in apply_bad_link_workaround()
328 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
332 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
333 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
334 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
338 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
341 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
344 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
353 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_rp_irq_handler()
354 struct pcie_port *pp = &pci->pp; in tegra_pcie_rp_irq_handler()
392 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
394 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & in tegra_pcie_rp_irq_handler()
404 dev_info(pci->dev, "CDM check complete\n"); in tegra_pcie_rp_irq_handler()
408 dev_err(pci->dev, "CDM comparison mismatch\n"); in tegra_pcie_rp_irq_handler()
412 dev_err(pci->dev, "CDM Logic error\n"); in tegra_pcie_rp_irq_handler()
417 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp); in tegra_pcie_rp_irq_handler()
452 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_ep_irq_thread()
455 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & in tegra_pcie_ep_irq_thread()
457 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); in tegra_pcie_ep_irq_thread()
460 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in tegra_pcie_ep_irq_thread()
469 /* 110us for both snoop and no-snoop */ in tegra_pcie_ep_irq_thread()
489 dev_err(pcie->dev, "Failed to send LTR message\n"); in tegra_pcie_ep_irq_thread()
498 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_hard_irq()
513 dev_dbg(pcie->dev, "Link is up with Host\n"); in tegra_pcie_ep_hard_irq()
532 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", in tegra_pcie_ep_hard_irq()
546 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_rd_own_conf()
563 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_wr_own_conf()
601 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l11()
603 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l11()
610 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l12()
612 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l12()
619 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]); in event_counter_prog()
624 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); in event_counter_prog()
625 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]); in event_counter_prog()
633 dev_get_drvdata(s->private); in aspm_state_cnt()
636 seq_printf(s, "Tx L0s entry count : %u\n", in aspm_state_cnt()
639 seq_printf(s, "Rx L0s entry count : %u\n", in aspm_state_cnt()
652 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], in aspm_state_cnt()
655 /* Re-enable counting */ in aspm_state_cnt()
658 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); in aspm_state_cnt()
665 struct dw_pcie *pci = &pcie->pci; in init_host_aspm()
669 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; in init_host_aspm()
671 /* Enable ASPM counters */ in init_host_aspm()
674 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val); in init_host_aspm()
677 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in init_host_aspm()
679 val |= (pcie->aspm_cmrt << 8); in init_host_aspm()
680 val |= (pcie->aspm_pwr_on_t << 19); in init_host_aspm()
681 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); in init_host_aspm()
683 /* Program L0s and L1 entrance latencies */ in init_host_aspm()
686 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); in init_host_aspm()
693 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, in init_debugfs()
718 if (pcie->enable_cdm_check) { in tegra_pcie_enable_system_interrupts()
729 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
731 pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >> in tegra_pcie_enable_system_interrupts()
734 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
737 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, in tegra_pcie_enable_system_interrupts()
805 struct dw_pcie *pci = &pcie->pci; in config_gen3_gen4_eq_presets()
809 for (i = 0; i < pcie->num_lanes; i++) { in config_gen3_gen4_eq_presets()
862 pp->bridge->ops = &tegra_pci_ops; in tegra_pcie_dw_host_init()
864 if (!pcie->pcie_cap_base) in tegra_pcie_dw_host_init()
865 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in tegra_pcie_dw_host_init()
887 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); in tegra_pcie_dw_host_init()
889 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT); in tegra_pcie_dw_host_init()
890 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); in tegra_pcie_dw_host_init()
896 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in tegra_pcie_dw_host_init()
897 if (!pcie->supports_clkreq) { in tegra_pcie_dw_host_init()
906 if (pcie->update_fc_fixup) { in tegra_pcie_dw_host_init()
912 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in tegra_pcie_dw_host_init()
921 struct pcie_port *pp = &pci->pp; in tegra_pcie_dw_start_link()
924 if (pcie->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_start_link()
925 enable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_start_link()
942 /* De-assert RST */ in tegra_pcie_dw_start_link()
970 dev_info(pci->dev, "Link is down in DLL"); in tegra_pcie_dw_start_link()
971 dev_info(pci->dev, "Trying again with DLFE disabled\n"); in tegra_pcie_dw_start_link()
977 reset_control_assert(pcie->core_rst); in tegra_pcie_dw_start_link()
978 reset_control_deassert(pcie->core_rst); in tegra_pcie_dw_start_link()
992 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & in tegra_pcie_dw_start_link()
994 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); in tegra_pcie_dw_start_link()
1004 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_dw_link_up()
1013 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_stop_link()
1028 unsigned int phy_count = pcie->phy_count; in tegra_pcie_disable_phy()
1030 while (phy_count--) { in tegra_pcie_disable_phy()
1031 phy_power_off(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1032 phy_exit(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1041 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_enable_phy()
1042 ret = phy_init(pcie->phys[i]); in tegra_pcie_enable_phy()
1046 ret = phy_power_on(pcie->phys[i]); in tegra_pcie_enable_phy()
1054 while (i--) { in tegra_pcie_enable_phy()
1055 phy_power_off(pcie->phys[i]); in tegra_pcie_enable_phy()
1057 phy_exit(pcie->phys[i]); in tegra_pcie_enable_phy()
1065 struct platform_device *pdev = to_platform_device(pcie->dev); in tegra_pcie_dw_parse_dt()
1066 struct device_node *np = pcie->dev->of_node; in tegra_pcie_dw_parse_dt()
1069 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in tegra_pcie_dw_parse_dt()
1070 if (!pcie->dbi_res) { in tegra_pcie_dw_parse_dt()
1071 dev_err(pcie->dev, "Failed to find \"dbi\" region\n"); in tegra_pcie_dw_parse_dt()
1072 return -ENODEV; in tegra_pcie_dw_parse_dt()
1075 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); in tegra_pcie_dw_parse_dt()
1077 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); in tegra_pcie_dw_parse_dt()
1081 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", in tegra_pcie_dw_parse_dt()
1082 &pcie->aspm_pwr_on_t); in tegra_pcie_dw_parse_dt()
1084 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", in tegra_pcie_dw_parse_dt()
1087 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", in tegra_pcie_dw_parse_dt()
1088 &pcie->aspm_l0s_enter_lat); in tegra_pcie_dw_parse_dt()
1090 dev_info(pcie->dev, in tegra_pcie_dw_parse_dt()
1091 "Failed to read ASPM L0s Entrance latency: %d\n", ret); in tegra_pcie_dw_parse_dt()
1093 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); in tegra_pcie_dw_parse_dt()
1095 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); in tegra_pcie_dw_parse_dt()
1099 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); in tegra_pcie_dw_parse_dt()
1101 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); in tegra_pcie_dw_parse_dt()
1105 ret = of_property_count_strings(np, "phy-names"); in tegra_pcie_dw_parse_dt()
1107 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", in tegra_pcie_dw_parse_dt()
1111 pcie->phy_count = ret; in tegra_pcie_dw_parse_dt()
1113 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) in tegra_pcie_dw_parse_dt()
1114 pcie->update_fc_fixup = true; in tegra_pcie_dw_parse_dt()
1116 pcie->supports_clkreq = in tegra_pcie_dw_parse_dt()
1117 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); in tegra_pcie_dw_parse_dt()
1119 pcie->enable_cdm_check = in tegra_pcie_dw_parse_dt()
1120 of_property_read_bool(np, "snps,enable-cdm-check"); in tegra_pcie_dw_parse_dt()
1122 if (pcie->mode == DW_PCIE_RC_TYPE) in tegra_pcie_dw_parse_dt()
1126 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); in tegra_pcie_dw_parse_dt()
1127 if (IS_ERR(pcie->pex_rst_gpiod)) { in tegra_pcie_dw_parse_dt()
1128 int err = PTR_ERR(pcie->pex_rst_gpiod); in tegra_pcie_dw_parse_dt()
1131 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1134 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1140 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, in tegra_pcie_dw_parse_dt()
1141 "nvidia,refclk-select", in tegra_pcie_dw_parse_dt()
1143 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { in tegra_pcie_dw_parse_dt()
1144 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); in tegra_pcie_dw_parse_dt()
1147 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1150 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1153 pcie->pex_refclk_sel_gpiod = NULL; in tegra_pcie_dw_parse_dt()
1166 /* Controller-5 doesn't need to have its state set by BPMP-FW */ in tegra_pcie_bpmp_set_ctrl_state()
1167 if (pcie->cid == 5) in tegra_pcie_bpmp_set_ctrl_state()
1174 req.controller_state.pcie_controller = pcie->cid; in tegra_pcie_bpmp_set_ctrl_state()
1184 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_ctrl_state()
1199 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1202 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1212 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_pll_state()
1217 struct pcie_port *pp = &pcie->pci.pp; in tegra_pcie_downstream_dev_to_D0()
1226 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, in tegra_pcie_downstream_dev_to_D0()
1230 list_for_each_entry(child, &pp->bridge->bus->children, node) { in tegra_pcie_downstream_dev_to_D0()
1232 if (child->parent == pp->bridge->bus) { in tegra_pcie_downstream_dev_to_D0()
1239 dev_err(pcie->dev, "Failed to find downstream devices\n"); in tegra_pcie_downstream_dev_to_D0()
1243 list_for_each_entry(pdev, &root_bus->devices, bus_list) { in tegra_pcie_downstream_dev_to_D0()
1244 if (PCI_SLOT(pdev->devfn) == 0) { in tegra_pcie_downstream_dev_to_D0()
1246 dev_err(pcie->dev, in tegra_pcie_downstream_dev_to_D0()
1248 dev_name(&pdev->dev)); in tegra_pcie_downstream_dev_to_D0()
1255 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); in tegra_pcie_get_slot_regulators()
1256 if (IS_ERR(pcie->slot_ctl_3v3)) { in tegra_pcie_get_slot_regulators()
1257 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) in tegra_pcie_get_slot_regulators()
1258 return PTR_ERR(pcie->slot_ctl_3v3); in tegra_pcie_get_slot_regulators()
1260 pcie->slot_ctl_3v3 = NULL; in tegra_pcie_get_slot_regulators()
1263 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); in tegra_pcie_get_slot_regulators()
1264 if (IS_ERR(pcie->slot_ctl_12v)) { in tegra_pcie_get_slot_regulators()
1265 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) in tegra_pcie_get_slot_regulators()
1266 return PTR_ERR(pcie->slot_ctl_12v); in tegra_pcie_get_slot_regulators()
1268 pcie->slot_ctl_12v = NULL; in tegra_pcie_get_slot_regulators()
1278 if (pcie->slot_ctl_3v3) { in tegra_pcie_enable_slot_regulators()
1279 ret = regulator_enable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1281 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1287 if (pcie->slot_ctl_12v) { in tegra_pcie_enable_slot_regulators()
1288 ret = regulator_enable(pcie->slot_ctl_12v); in tegra_pcie_enable_slot_regulators()
1290 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1298 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) in tegra_pcie_enable_slot_regulators()
1301 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) in tegra_pcie_enable_slot_regulators()
1307 if (pcie->slot_ctl_3v3) in tegra_pcie_enable_slot_regulators()
1308 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1314 if (pcie->slot_ctl_12v) in tegra_pcie_disable_slot_regulators()
1315 regulator_disable(pcie->slot_ctl_12v); in tegra_pcie_disable_slot_regulators()
1316 if (pcie->slot_ctl_3v3) in tegra_pcie_disable_slot_regulators()
1317 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_disable_slot_regulators()
1328 dev_err(pcie->dev, in tegra_pcie_config_controller()
1329 "Failed to enable controller %u: %d\n", pcie->cid, ret); in tegra_pcie_config_controller()
1337 ret = regulator_enable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1339 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); in tegra_pcie_config_controller()
1343 ret = clk_prepare_enable(pcie->core_clk); in tegra_pcie_config_controller()
1345 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); in tegra_pcie_config_controller()
1349 ret = reset_control_deassert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1351 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", in tegra_pcie_config_controller()
1367 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); in tegra_pcie_config_controller()
1372 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1387 if (!pcie->supports_clkreq) { in tegra_pcie_config_controller()
1396 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1399 reset_control_deassert(pcie->core_rst); in tegra_pcie_config_controller()
1404 reset_control_assert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1406 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_config_controller()
1408 regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1421 ret = reset_control_assert(pcie->core_rst); in tegra_pcie_unconfig_controller()
1423 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1427 ret = reset_control_assert(pcie->core_apb_rst); in tegra_pcie_unconfig_controller()
1429 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); in tegra_pcie_unconfig_controller()
1431 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_unconfig_controller()
1433 ret = regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_unconfig_controller()
1435 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); in tegra_pcie_unconfig_controller()
1441 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", in tegra_pcie_unconfig_controller()
1442 pcie->cid, ret); in tegra_pcie_unconfig_controller()
1447 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_init_controller()
1448 struct pcie_port *pp = &pci->pp; in tegra_pcie_init_controller()
1455 pp->ops = &tegra_pcie_dw_host_ops; in tegra_pcie_init_controller()
1459 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); in tegra_pcie_init_controller()
1474 if (!tegra_pcie_dw_link_up(&pcie->pci)) in tegra_pcie_try_link_l2()
1481 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, in tegra_pcie_try_link_l2()
1491 if (!tegra_pcie_dw_link_up(&pcie->pci)) { in tegra_pcie_dw_pme_turnoff()
1492 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); in tegra_pcie_dw_pme_turnoff()
1507 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); in tegra_pcie_dw_pme_turnoff()
1519 * Some cards do not go to detect state even after de-asserting in tegra_pcie_dw_pme_turnoff()
1520 * PERST#. So, de-assert LTSSM to bring link to detect state. in tegra_pcie_dw_pme_turnoff()
1522 data = readl(pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1524 writel(data, pcie->appl_base + APPL_CTRL); in tegra_pcie_dw_pme_turnoff()
1526 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, in tegra_pcie_dw_pme_turnoff()
1534 dev_info(pcie->dev, "Link didn't go to detect state\n"); in tegra_pcie_dw_pme_turnoff()
1537 * DBI registers may not be accessible after this as PLL-E would be in tegra_pcie_dw_pme_turnoff()
1551 dw_pcie_host_deinit(&pcie->pci.pp); in tegra_pcie_deinit_controller()
1558 struct device *dev = pcie->dev; in tegra_pcie_config_rp()
1583 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); in tegra_pcie_config_rp()
1584 if (!pcie->link_state) { in tegra_pcie_config_rp()
1585 ret = -ENOMEDIUM; in tegra_pcie_config_rp()
1589 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in tegra_pcie_config_rp()
1591 ret = -ENOMEM; in tegra_pcie_config_rp()
1595 pcie->debugfs = debugfs_create_dir(name, NULL); in tegra_pcie_config_rp()
1613 if (pcie->ep_state == EP_STATE_DISABLED) in pex_ep_event_pex_rst_assert()
1621 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, in pex_ep_event_pex_rst_assert()
1627 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); in pex_ep_event_pex_rst_assert()
1629 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_assert()
1633 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_assert()
1635 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_assert()
1637 pm_runtime_put_sync(pcie->dev); in pex_ep_event_pex_rst_assert()
1641 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); in pex_ep_event_pex_rst_assert()
1643 pcie->ep_state = EP_STATE_DISABLED; in pex_ep_event_pex_rst_assert()
1644 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); in pex_ep_event_pex_rst_assert()
1649 struct dw_pcie *pci = &pcie->pci; in pex_ep_event_pex_rst_deassert()
1650 struct dw_pcie_ep *ep = &pci->ep; in pex_ep_event_pex_rst_deassert()
1651 struct device *dev = pcie->dev; in pex_ep_event_pex_rst_deassert()
1655 if (pcie->ep_state == EP_STATE_ENABLED) in pex_ep_event_pex_rst_deassert()
1671 ret = clk_prepare_enable(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1677 ret = reset_control_deassert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1729 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in pex_ep_event_pex_rst_deassert()
1732 appl_writel(pcie, pcie->atu_dma_res->start & in pex_ep_event_pex_rst_deassert()
1747 reset_control_deassert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1749 if (pcie->update_fc_fixup) { in pex_ep_event_pex_rst_deassert()
1759 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in pex_ep_event_pex_rst_deassert()
1760 if (!pcie->supports_clkreq) { in pex_ep_event_pex_rst_deassert()
1769 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in pex_ep_event_pex_rst_deassert()
1771 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in pex_ep_event_pex_rst_deassert()
1773 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1776 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1792 pcie->ep_state = EP_STATE_ENABLED; in pex_ep_event_pex_rst_deassert()
1798 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1801 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1803 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1814 if (gpiod_get_value(pcie->pex_rst_gpiod)) in tegra_pcie_ep_pex_rst_irq()
1826 return -EINVAL; in tegra_pcie_ep_raise_legacy_irq()
1837 return -EINVAL; in tegra_pcie_ep_raise_msi_irq()
1846 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_raise_msix_irq()
1848 writel(irq, ep->msi_mem); in tegra_pcie_ep_raise_msix_irq()
1871 dev_err(pci->dev, "Unknown IRQ type\n"); in tegra_pcie_ep_raise_irq()
1872 return -EPERM; in tegra_pcie_ep_raise_irq()
1902 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_config_ep()
1903 struct device *dev = pcie->dev; in tegra_pcie_config_ep()
1908 ep = &pci->ep; in tegra_pcie_config_ep()
1909 ep->ops = &pcie_ep_ops; in tegra_pcie_config_ep()
1911 ep->page_size = SZ_64K; in tegra_pcie_config_ep()
1913 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); in tegra_pcie_config_ep()
1920 ret = gpiod_to_irq(pcie->pex_rst_gpiod); in tegra_pcie_config_ep()
1925 pcie->pex_rst_irq = (unsigned int)ret; in tegra_pcie_config_ep()
1928 pcie->cid); in tegra_pcie_config_ep()
1931 return -ENOMEM; in tegra_pcie_config_ep()
1934 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); in tegra_pcie_config_ep()
1936 pcie->ep_state = EP_STATE_DISABLED; in tegra_pcie_config_ep()
1938 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, in tegra_pcie_config_ep()
1963 struct device *dev = &pdev->dev; in tegra_pcie_dw_probe()
1977 return -ENOMEM; in tegra_pcie_dw_probe()
1979 pci = &pcie->pci; in tegra_pcie_dw_probe()
1980 pci->dev = &pdev->dev; in tegra_pcie_dw_probe()
1981 pci->ops = &tegra_dw_pcie_ops; in tegra_pcie_dw_probe()
1982 pci->n_fts[0] = N_FTS_VAL; in tegra_pcie_dw_probe()
1983 pci->n_fts[1] = FTS_VAL; in tegra_pcie_dw_probe()
1984 pci->version = 0x490A; in tegra_pcie_dw_probe()
1986 pp = &pci->pp; in tegra_pcie_dw_probe()
1987 pp->num_vectors = MAX_MSI_IRQS; in tegra_pcie_dw_probe()
1988 pcie->dev = &pdev->dev; in tegra_pcie_dw_probe()
1989 pcie->mode = (enum dw_pcie_device_mode)data->mode; in tegra_pcie_dw_probe()
1995 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2008 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2017 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_probe()
2018 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); in tegra_pcie_dw_probe()
2020 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); in tegra_pcie_dw_probe()
2021 if (IS_ERR(pcie->pex_ctl_supply)) { in tegra_pcie_dw_probe()
2022 ret = PTR_ERR(pcie->pex_ctl_supply); in tegra_pcie_dw_probe()
2023 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2025 PTR_ERR(pcie->pex_ctl_supply)); in tegra_pcie_dw_probe()
2029 pcie->core_clk = devm_clk_get(dev, "core"); in tegra_pcie_dw_probe()
2030 if (IS_ERR(pcie->core_clk)) { in tegra_pcie_dw_probe()
2032 PTR_ERR(pcie->core_clk)); in tegra_pcie_dw_probe()
2033 return PTR_ERR(pcie->core_clk); in tegra_pcie_dw_probe()
2036 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, in tegra_pcie_dw_probe()
2038 if (!pcie->appl_res) { in tegra_pcie_dw_probe()
2040 return -ENODEV; in tegra_pcie_dw_probe()
2043 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); in tegra_pcie_dw_probe()
2044 if (IS_ERR(pcie->appl_base)) in tegra_pcie_dw_probe()
2045 return PTR_ERR(pcie->appl_base); in tegra_pcie_dw_probe()
2047 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); in tegra_pcie_dw_probe()
2048 if (IS_ERR(pcie->core_apb_rst)) { in tegra_pcie_dw_probe()
2050 PTR_ERR(pcie->core_apb_rst)); in tegra_pcie_dw_probe()
2051 return PTR_ERR(pcie->core_apb_rst); in tegra_pcie_dw_probe()
2054 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); in tegra_pcie_dw_probe()
2056 return -ENOMEM; in tegra_pcie_dw_probe()
2058 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_dw_probe()
2059 name = kasprintf(GFP_KERNEL, "p2u-%u", i); in tegra_pcie_dw_probe()
2062 return -ENOMEM; in tegra_pcie_dw_probe()
2068 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2074 pcie->phys = phys; in tegra_pcie_dw_probe()
2080 return -ENODEV; in tegra_pcie_dw_probe()
2082 pcie->atu_dma_res = atu_dma_res; in tegra_pcie_dw_probe()
2084 pci->atu_size = resource_size(atu_dma_res); in tegra_pcie_dw_probe()
2085 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); in tegra_pcie_dw_probe()
2086 if (IS_ERR(pci->atu_base)) in tegra_pcie_dw_probe()
2087 return PTR_ERR(pci->atu_base); in tegra_pcie_dw_probe()
2089 pcie->core_rst = devm_reset_control_get(dev, "core"); in tegra_pcie_dw_probe()
2090 if (IS_ERR(pcie->core_rst)) { in tegra_pcie_dw_probe()
2092 PTR_ERR(pcie->core_rst)); in tegra_pcie_dw_probe()
2093 return PTR_ERR(pcie->core_rst); in tegra_pcie_dw_probe()
2096 pp->irq = platform_get_irq_byname(pdev, "intr"); in tegra_pcie_dw_probe()
2097 if (pp->irq < 0) in tegra_pcie_dw_probe()
2098 return pp->irq; in tegra_pcie_dw_probe()
2100 pcie->bpmp = tegra_bpmp_get(dev); in tegra_pcie_dw_probe()
2101 if (IS_ERR(pcie->bpmp)) in tegra_pcie_dw_probe()
2102 return PTR_ERR(pcie->bpmp); in tegra_pcie_dw_probe()
2106 switch (pcie->mode) { in tegra_pcie_dw_probe()
2108 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, in tegra_pcie_dw_probe()
2109 IRQF_SHARED, "tegra-pcie-intr", pcie); in tegra_pcie_dw_probe()
2111 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2117 if (ret && ret != -ENOMEDIUM) in tegra_pcie_dw_probe()
2124 ret = devm_request_threaded_irq(dev, pp->irq, in tegra_pcie_dw_probe()
2128 "tegra-pcie-ep-intr", pcie); in tegra_pcie_dw_probe()
2130 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2141 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode); in tegra_pcie_dw_probe()
2145 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2153 if (!pcie->link_state) in tegra_pcie_dw_remove()
2156 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_remove()
2158 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_remove()
2159 pm_runtime_disable(pcie->dev); in tegra_pcie_dw_remove()
2160 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_remove()
2161 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_remove()
2162 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); in tegra_pcie_dw_remove()
2172 if (!pcie->link_state) in tegra_pcie_dw_suspend_late()
2189 if (!pcie->link_state) in tegra_pcie_dw_suspend_noirq()
2193 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci, in tegra_pcie_dw_suspend_noirq()
2207 if (!pcie->link_state) in tegra_pcie_dw_resume_noirq()
2214 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2220 dw_pcie_setup_rc(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2222 ret = tegra_pcie_dw_start_link(&pcie->pci); in tegra_pcie_dw_resume_noirq()
2227 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN, in tegra_pcie_dw_resume_noirq()
2228 pcie->msi_ctrl_int); in tegra_pcie_dw_resume_noirq()
2242 if (pcie->mode == DW_PCIE_EP_TYPE) { in tegra_pcie_dw_resume_early()
2244 return -ENOTSUPP; in tegra_pcie_dw_resume_early()
2247 if (!pcie->link_state) in tegra_pcie_dw_resume_early()
2266 if (!pcie->link_state) in tegra_pcie_dw_shutdown()
2269 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_shutdown()
2272 disable_irq(pcie->pci.pp.irq); in tegra_pcie_dw_shutdown()
2274 disable_irq(pcie->pci.pp.msi_irq); in tegra_pcie_dw_shutdown()
2290 .compatible = "nvidia,tegra194-pcie",
2294 .compatible = "nvidia,tegra194-pcie-ep",
2312 .name = "tegra194-pcie",