332 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_1_0()
338 		dev_err(dev, "cannot deassert ahb reset\n");  in qcom_pcie_init_2_1_0()
344 		dev_err(dev, "cannot deassert ext reset\n");  in qcom_pcie_init_2_1_0()
350 		dev_err(dev, "cannot deassert phy reset\n");  in qcom_pcie_init_2_1_0()
356 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_1_0()
362 		dev_err(dev, "cannot deassert por reset\n");  in qcom_pcie_init_2_1_0()
368 		dev_err(dev, "cannot deassert axi reset\n");  in qcom_pcie_init_2_1_0()
489 		dev_err(dev, "cannot deassert core reset\n");  in qcom_pcie_init_1_0_0()
495 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_1_0_0()
501 		dev_err(dev, "cannot prepare/enable iface clock\n");  in qcom_pcie_init_1_0_0()
507 		dev_err(dev, "cannot prepare/enable master_bus clock\n");  in qcom_pcie_init_1_0_0()
513 		dev_err(dev, "cannot prepare/enable slave_bus clock\n");  in qcom_pcie_init_1_0_0()
519 		dev_err(dev, "cannot enable vdda regulator\n");  in qcom_pcie_init_1_0_0()
621 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_3_2()
627 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_2_3_2()
633 		dev_err(dev, "cannot prepare/enable cfg clock\n");  in qcom_pcie_init_2_3_2()
639 		dev_err(dev, "cannot prepare/enable master clock\n");  in qcom_pcie_init_2_3_2()
645 		dev_err(dev, "cannot prepare/enable slave clock\n");  in qcom_pcie_init_2_3_2()
694 		dev_err(dev, "cannot prepare/enable pipe clock\n");  in qcom_pcie_post_init_2_3_2()
810 		dev_err(dev, "cannot assert axi master reset\n");  in qcom_pcie_init_2_4_0()
816 		dev_err(dev, "cannot assert axi slave reset\n");  in qcom_pcie_init_2_4_0()
824 		dev_err(dev, "cannot assert pipe reset\n");  in qcom_pcie_init_2_4_0()
830 		dev_err(dev, "cannot assert pipe sticky reset\n");  in qcom_pcie_init_2_4_0()
836 		dev_err(dev, "cannot assert phy reset\n");  in qcom_pcie_init_2_4_0()
842 		dev_err(dev, "cannot assert phy ahb reset\n");  in qcom_pcie_init_2_4_0()
850 		dev_err(dev, "cannot assert axi master sticky reset\n");  in qcom_pcie_init_2_4_0()
856 		dev_err(dev, "cannot assert power reset\n");  in qcom_pcie_init_2_4_0()
862 		dev_err(dev, "cannot assert ahb reset\n");  in qcom_pcie_init_2_4_0()
870 		dev_err(dev, "cannot deassert phy ahb reset\n");  in qcom_pcie_init_2_4_0()
876 		dev_err(dev, "cannot deassert phy reset\n");  in qcom_pcie_init_2_4_0()
882 		dev_err(dev, "cannot deassert pipe reset\n");  in qcom_pcie_init_2_4_0()
888 		dev_err(dev, "cannot deassert pipe sticky reset\n");  in qcom_pcie_init_2_4_0()
896 		dev_err(dev, "cannot deassert axi master reset\n");  in qcom_pcie_init_2_4_0()
902 		dev_err(dev, "cannot deassert axi master sticky reset\n");  in qcom_pcie_init_2_4_0()
908 		dev_err(dev, "cannot deassert axi slave reset\n");  in qcom_pcie_init_2_4_0()
914 		dev_err(dev, "cannot deassert power reset\n");  in qcom_pcie_init_2_4_0()
920 		dev_err(dev, "cannot deassert ahb reset\n");  in qcom_pcie_init_2_4_0()
1060 		dev_err(dev, "cannot prepare/enable core clock\n");  in qcom_pcie_init_2_3_3()
1066 		dev_err(dev, "cannot prepare/enable core clock\n");  in qcom_pcie_init_2_3_3()
1072 		dev_err(dev, "cannot prepare/enable axi slave clock\n");  in qcom_pcie_init_2_3_3()
1078 		dev_err(dev, "cannot prepare/enable ahb clock\n");  in qcom_pcie_init_2_3_3()
1084 		dev_err(dev, "cannot prepare/enable aux clock\n");  in qcom_pcie_init_2_3_3()
1184 		dev_err(dev, "cannot enable regulators\n");  in qcom_pcie_init_2_7_0()
1194 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_7_0()
1202 		dev_err(dev, "cannot deassert pci reset\n");  in qcom_pcie_init_2_7_0()
1208 		dev_err(dev, "cannot prepare/enable pipe clock\n");  in qcom_pcie_init_2_7_0()
1533 		dev_err(dev, "cannot initialize host\n");  in qcom_pcie_probe()