1 // SPDX-License-Identifier: GPL-2.0
3  * PCIe host controller driver for Intel Gateway SoCs
18 #include "pcie-designware.h"
20 #define PORT_AFR_N_FTS_GEN12_DFT	(SZ_128 - 1)
24 /* PCIe Application logic Registers */
88 	writel(val, lpp->app_base + ofs);  in pcie_app_wr()
94 	pcie_update_bits(lpp->app_base, ofs, mask, val);  in pcie_app_wr_mask()
99 	return dw_pcie_readl_dbi(&lpp->pci, ofs);  in pcie_rc_cfg_rd()
104 	dw_pcie_writel_dbi(&lpp->pci, ofs, val);  in pcie_rc_cfg_wr()
110 	pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val);  in pcie_rc_cfg_wr_mask()
127 	u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);  in intel_pcie_link_setup()
137 	switch (pci->link_gen) {  in intel_pcie_init_n_fts()
139 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;  in intel_pcie_init_n_fts()
142 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN4;  in intel_pcie_init_n_fts()
145 		pci->n_fts[1] = PORT_AFR_N_FTS_GEN12_DFT;  in intel_pcie_init_n_fts()
148 	pci->n_fts[0] = PORT_AFR_N_FTS_GEN12_DFT;  in intel_pcie_init_n_fts()
153 	struct device *dev = lpp->pci.dev;  in intel_pcie_ep_rst_init()
156 	lpp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);  in intel_pcie_ep_rst_init()
157 	if (IS_ERR(lpp->reset_gpio)) {  in intel_pcie_ep_rst_init()
158 		ret = PTR_ERR(lpp->reset_gpio);  in intel_pcie_ep_rst_init()
159 		if (ret != -EPROBE_DEFER)  in intel_pcie_ep_rst_init()
160 			dev_err(dev, "Failed to request PCIe GPIO: %d\n", ret);  in intel_pcie_ep_rst_init()
172 	reset_control_assert(lpp->core_rst);  in intel_pcie_core_rst_assert()
178 	 * One micro-second delay to make sure the reset pulse  in intel_pcie_core_rst_deassert()
182 	reset_control_deassert(lpp->core_rst);  in intel_pcie_core_rst_deassert()
193 	gpiod_set_value_cansleep(lpp->reset_gpio, 1);  in intel_pcie_device_rst_assert()
198 	msleep(lpp->rst_intrvl);  in intel_pcie_device_rst_deassert()
199 	gpiod_set_value_cansleep(lpp->reset_gpio, 0);  in intel_pcie_device_rst_deassert()
211 	struct dw_pcie *pci = &lpp->pci;  in intel_pcie_get_resources()
212 	struct device *dev = pci->dev;  in intel_pcie_get_resources()
215 	lpp->core_clk = devm_clk_get(dev, NULL);  in intel_pcie_get_resources()
216 	if (IS_ERR(lpp->core_clk)) {  in intel_pcie_get_resources()
217 		ret = PTR_ERR(lpp->core_clk);  in intel_pcie_get_resources()
218 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
223 	lpp->core_rst = devm_reset_control_get(dev, NULL);  in intel_pcie_get_resources()
224 	if (IS_ERR(lpp->core_rst)) {  in intel_pcie_get_resources()
225 		ret = PTR_ERR(lpp->core_rst);  in intel_pcie_get_resources()
226 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
231 	ret = device_property_read_u32(dev, "reset-assert-ms",  in intel_pcie_get_resources()
232 				       &lpp->rst_intrvl);  in intel_pcie_get_resources()
234 		lpp->rst_intrvl = RESET_INTERVAL_MS;  in intel_pcie_get_resources()
236 	lpp->app_base = devm_platform_ioremap_resource_byname(pdev, "app");  in intel_pcie_get_resources()
237 	if (IS_ERR(lpp->app_base))  in intel_pcie_get_resources()
238 		return PTR_ERR(lpp->app_base);  in intel_pcie_get_resources()
240 	lpp->phy = devm_phy_get(dev, "pcie");  in intel_pcie_get_resources()
241 	if (IS_ERR(lpp->phy)) {  in intel_pcie_get_resources()
242 		ret = PTR_ERR(lpp->phy);  in intel_pcie_get_resources()
243 		if (ret != -EPROBE_DEFER)  in intel_pcie_get_resources()
244 			dev_err(dev, "Couldn't get pcie-phy: %d\n", ret);  in intel_pcie_get_resources()
255 	struct dw_pcie *pci = &lpp->pci;  in intel_pcie_wait_l2()
257 	if (pci->link_gen < 3)  in intel_pcie_wait_l2()
265 	ret = readl_poll_timeout(lpp->app_base + PCIE_APP_PMC, value,  in intel_pcie_wait_l2()
269 		dev_err(lpp->pci.dev, "PCIe link enter L2 timeout!\n");  in intel_pcie_wait_l2()
276 	if (dw_pcie_link_up(&lpp->pci))  in intel_pcie_turn_off()
287 	struct dw_pcie *pci = &lpp->pci;  in intel_pcie_host_setup()
292 	ret = phy_init(lpp->phy);  in intel_pcie_host_setup()
298 	ret = clk_prepare_enable(lpp->core_clk);  in intel_pcie_host_setup()
300 		dev_err(lpp->pci.dev, "Core clock enable failed: %d\n", ret);  in intel_pcie_host_setup()
304 	pci->atu_base = pci->dbi_base + 0xC0000;  in intel_pcie_host_setup()
309 	dw_pcie_setup_rc(&pci->pp);  in intel_pcie_host_setup()
326 	clk_disable_unprepare(lpp->core_clk);  in intel_pcie_host_setup()
329 	phy_exit(lpp->phy);  in intel_pcie_host_setup()
338 	clk_disable_unprepare(lpp->core_clk);  in __intel_pcie_remove()
340 	phy_exit(lpp->phy);  in __intel_pcie_remove()
346 	struct pcie_port *pp = &lpp->pci.pp;  in intel_pcie_remove()
364 	phy_exit(lpp->phy);  in intel_pcie_suspend_noirq()
365 	clk_disable_unprepare(lpp->core_clk);  in intel_pcie_suspend_noirq()
379 	struct intel_pcie_port *lpp = dev_get_drvdata(pci->dev);  in intel_pcie_rc_init()
384 static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr)  in intel_pcie_cpu_addr()  argument
404 	struct device *dev = &pdev->dev;  in intel_pcie_probe()
412 		return -ENOMEM;  in intel_pcie_probe()
415 	pci = &lpp->pci;  in intel_pcie_probe()
416 	pci->dev = dev;  in intel_pcie_probe()
417 	pp = &pci->pp;  in intel_pcie_probe()
429 		return -ENODEV;  in intel_pcie_probe()
431 	pci->ops = &intel_pcie_ops;  in intel_pcie_probe()
432 	pci->version = data->pcie_ver;  in intel_pcie_probe()
433 	pp->ops = &intel_pcie_dw_ops;  in intel_pcie_probe()
450 	{ .compatible = "intel,lgm-pcie", .data = &pcie_data },
458 		.name = "intel-gw-pcie",