Lines Matching +full:0 +full:x8c8
43 #define SIFIVE_DEVICESRESETREG 0x28
45 #define PCIEX8MGMT_PERST_N 0x0
46 #define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10
47 #define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18
48 #define PCIEX8MGMT_DEVICE_TYPE 0x708
49 #define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860
50 #define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870
51 #define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878
52 #define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880
53 #define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888
54 #define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890
55 #define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898
56 #define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0
57 #define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0
58 #define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8
59 #define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0
60 #define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8
61 #define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0
62 #define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8
64 #define PCIEX8MGMT_PHY_CDR_TRACK_EN BIT(0)
75 #define PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 0x1008
76 #define PCIEX8MGMT_PHY_LANE_OFF 0x100
77 #define PCIEX8MGMT_PHY_LANE0_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 0)
78 #define PCIEX8MGMT_PHY_LANE1_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 1)
79 #define PCIEX8MGMT_PHY_LANE2_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 2)
80 #define PCIEX8MGMT_PHY_LANE3_BASE (PCIEX8MGMT_PHY_LANEN_DIG_ASIC_RX_OVRD_IN_3 + 0x100 * 3)
85 gpiod_set_value_cansleep(afp->reset, 0); in fu740_pcie_assert_reset()
87 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N); in fu740_pcie_assert_reset()
93 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N); in fu740_pcie_deassert_reset()
149 writel_relaxed(0, phy_cr_para_wr_en); in fu740_phyregwrite()
160 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL); in fu740_pcie_init_phy()
161 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL); in fu740_pcie_init_phy()
170 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); in fu740_pcie_init_phy()
171 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); in fu740_pcie_init_phy()
172 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); in fu740_pcie_init_phy()
173 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp); in fu740_pcie_init_phy()
186 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE); in fu740_pcie_start_link()
187 return 0; in fu740_pcie_start_link()
211 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); in fu740_pcie_host_init()
225 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST); in fu740_pcie_host_init()
229 writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE); in fu740_pcie_host_init()
231 return 0; in fu740_pcie_host_init()