Lines Matching full:pci
16 #include "../../pci.h"
21 * are for configuring host controllers, which are bridges *to* PCI devices but
22 * are not PCI devices themselves.
24 static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, in __dw_pcie_find_next_cap() argument
33 reg = dw_pcie_readw_dbi(pci, cap_ptr); in __dw_pcie_find_next_cap()
43 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); in __dw_pcie_find_next_cap()
46 u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) in dw_pcie_find_capability() argument
51 reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); in dw_pcie_find_capability()
54 return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); in dw_pcie_find_capability()
58 static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, in dw_pcie_find_next_ext_capability() argument
71 header = dw_pcie_readl_dbi(pci, pos); in dw_pcie_find_next_ext_capability()
87 header = dw_pcie_readl_dbi(pci, pos); in dw_pcie_find_next_ext_capability()
93 u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) in dw_pcie_find_ext_capability() argument
95 return dw_pcie_find_next_ext_capability(pci, 0, cap); in dw_pcie_find_ext_capability()
139 u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size) in dw_pcie_read_dbi() argument
144 if (pci->ops && pci->ops->read_dbi) in dw_pcie_read_dbi()
145 return pci->ops->read_dbi(pci, pci->dbi_base, reg, size); in dw_pcie_read_dbi()
147 ret = dw_pcie_read(pci->dbi_base + reg, size, &val); in dw_pcie_read_dbi()
149 dev_err(pci->dev, "Read DBI address failed\n"); in dw_pcie_read_dbi()
155 void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val) in dw_pcie_write_dbi() argument
159 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_write_dbi()
160 pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val); in dw_pcie_write_dbi()
164 ret = dw_pcie_write(pci->dbi_base + reg, size, val); in dw_pcie_write_dbi()
166 dev_err(pci->dev, "Write DBI address failed\n"); in dw_pcie_write_dbi()
170 void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val) in dw_pcie_write_dbi2() argument
174 if (pci->ops && pci->ops->write_dbi2) { in dw_pcie_write_dbi2()
175 pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val); in dw_pcie_write_dbi2()
179 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val); in dw_pcie_write_dbi2()
181 dev_err(pci->dev, "write DBI address failed\n"); in dw_pcie_write_dbi2()
184 static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg) in dw_pcie_readl_atu() argument
189 if (pci->ops && pci->ops->read_dbi) in dw_pcie_readl_atu()
190 return pci->ops->read_dbi(pci, pci->atu_base, reg, 4); in dw_pcie_readl_atu()
192 ret = dw_pcie_read(pci->atu_base + reg, 4, &val); in dw_pcie_readl_atu()
194 dev_err(pci->dev, "Read ATU address failed\n"); in dw_pcie_readl_atu()
199 static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) in dw_pcie_writel_atu() argument
203 if (pci->ops && pci->ops->write_dbi) { in dw_pcie_writel_atu()
204 pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val); in dw_pcie_writel_atu()
208 ret = dw_pcie_write(pci->atu_base + reg, 4, val); in dw_pcie_writel_atu()
210 dev_err(pci->dev, "Write ATU address failed\n"); in dw_pcie_writel_atu()
213 static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) in dw_pcie_readl_ob_unroll() argument
217 return dw_pcie_readl_atu(pci, offset + reg); in dw_pcie_readl_ob_unroll()
220 static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg, in dw_pcie_writel_ob_unroll() argument
225 dw_pcie_writel_atu(pci, offset + reg, val); in dw_pcie_writel_ob_unroll()
241 * Digest as there is no way the PCI core AER code could program in dw_pcie_enable_ecrc()
269 static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no, in dw_pcie_prog_outbound_atu_unroll() argument
277 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, in dw_pcie_prog_outbound_atu_unroll()
279 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, in dw_pcie_prog_outbound_atu_unroll()
281 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT, in dw_pcie_prog_outbound_atu_unroll()
283 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT, in dw_pcie_prog_outbound_atu_unroll()
285 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, in dw_pcie_prog_outbound_atu_unroll()
287 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, in dw_pcie_prog_outbound_atu_unroll()
292 if (pci->version == 0x490A) in dw_pcie_prog_outbound_atu_unroll()
294 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, val); in dw_pcie_prog_outbound_atu_unroll()
295 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in dw_pcie_prog_outbound_atu_unroll()
303 val = dw_pcie_readl_ob_unroll(pci, index, in dw_pcie_prog_outbound_atu_unroll()
310 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in dw_pcie_prog_outbound_atu_unroll()
313 static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, in __dw_pcie_prog_outbound_atu() argument
319 if (pci->ops && pci->ops->cpu_addr_fixup) in __dw_pcie_prog_outbound_atu()
320 cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); in __dw_pcie_prog_outbound_atu()
322 if (pci->iatu_unroll_enabled) { in __dw_pcie_prog_outbound_atu()
323 dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type, in __dw_pcie_prog_outbound_atu()
328 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, in __dw_pcie_prog_outbound_atu()
330 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE, in __dw_pcie_prog_outbound_atu()
332 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE, in __dw_pcie_prog_outbound_atu()
334 dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, in __dw_pcie_prog_outbound_atu()
336 if (pci->version >= 0x460A) in __dw_pcie_prog_outbound_atu()
337 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT, in __dw_pcie_prog_outbound_atu()
339 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, in __dw_pcie_prog_outbound_atu()
341 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, in __dw_pcie_prog_outbound_atu()
344 val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ? in __dw_pcie_prog_outbound_atu()
346 if (pci->version == 0x490A) in __dw_pcie_prog_outbound_atu()
348 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val); in __dw_pcie_prog_outbound_atu()
349 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); in __dw_pcie_prog_outbound_atu()
356 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); in __dw_pcie_prog_outbound_atu()
362 dev_err(pci->dev, "Outbound iATU is not being enabled\n"); in __dw_pcie_prog_outbound_atu()
365 void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, in dw_pcie_prog_outbound_atu() argument
368 __dw_pcie_prog_outbound_atu(pci, 0, index, type, in dw_pcie_prog_outbound_atu()
372 void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, in dw_pcie_prog_ep_outbound_atu() argument
376 __dw_pcie_prog_outbound_atu(pci, func_no, index, type, in dw_pcie_prog_ep_outbound_atu()
380 static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg) in dw_pcie_readl_ib_unroll() argument
384 return dw_pcie_readl_atu(pci, offset + reg); in dw_pcie_readl_ib_unroll()
387 static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg, in dw_pcie_writel_ib_unroll() argument
392 dw_pcie_writel_atu(pci, offset + reg, val); in dw_pcie_writel_ib_unroll()
395 static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no, in dw_pcie_prog_inbound_atu_unroll() argument
402 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, in dw_pcie_prog_inbound_atu_unroll()
404 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, in dw_pcie_prog_inbound_atu_unroll()
418 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type | in dw_pcie_prog_inbound_atu_unroll()
420 dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, in dw_pcie_prog_inbound_atu_unroll()
430 val = dw_pcie_readl_ib_unroll(pci, index, in dw_pcie_prog_inbound_atu_unroll()
437 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu_unroll()
442 int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, in dw_pcie_prog_inbound_atu() argument
449 if (pci->iatu_unroll_enabled) in dw_pcie_prog_inbound_atu()
450 return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar, in dw_pcie_prog_inbound_atu()
453 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | in dw_pcie_prog_inbound_atu()
455 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
456 dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr)); in dw_pcie_prog_inbound_atu()
469 dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type | in dw_pcie_prog_inbound_atu()
471 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE | in dw_pcie_prog_inbound_atu()
480 val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); in dw_pcie_prog_inbound_atu()
486 dev_err(pci->dev, "Inbound iATU is not being enabled\n"); in dw_pcie_prog_inbound_atu()
491 void dw_pcie_disable_atu(struct dw_pcie *pci, int index, in dw_pcie_disable_atu() argument
507 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index); in dw_pcie_disable_atu()
508 dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE); in dw_pcie_disable_atu()
511 int dw_pcie_wait_for_link(struct dw_pcie *pci) in dw_pcie_wait_for_link() argument
517 if (dw_pcie_link_up(pci)) { in dw_pcie_wait_for_link()
518 dev_info(pci->dev, "Link up\n"); in dw_pcie_wait_for_link()
524 dev_info(pci->dev, "Phy link never came up\n"); in dw_pcie_wait_for_link()
530 int dw_pcie_link_up(struct dw_pcie *pci) in dw_pcie_link_up() argument
534 if (pci->ops && pci->ops->link_up) in dw_pcie_link_up()
535 return pci->ops->link_up(pci); in dw_pcie_link_up()
537 val = readl(pci->dbi_base + PCIE_PORT_DEBUG1); in dw_pcie_link_up()
542 void dw_pcie_upconfig_setup(struct dw_pcie *pci) in dw_pcie_upconfig_setup() argument
546 val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL); in dw_pcie_upconfig_setup()
548 dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val); in dw_pcie_upconfig_setup()
552 static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) in dw_pcie_link_set_max_speed() argument
555 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); in dw_pcie_link_set_max_speed()
557 cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); in dw_pcie_link_set_max_speed()
558 ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); in dw_pcie_link_set_max_speed()
581 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); in dw_pcie_link_set_max_speed()
584 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); in dw_pcie_link_set_max_speed()
588 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) in dw_pcie_iatu_unroll_enabled() argument
592 val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); in dw_pcie_iatu_unroll_enabled()
599 static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci) in dw_pcie_iatu_detect_regions_unroll() argument
604 max_region = min((int)pci->atu_size / 512, 256); in dw_pcie_iatu_detect_regions_unroll()
607 dw_pcie_writel_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET, in dw_pcie_iatu_detect_regions_unroll()
610 val = dw_pcie_readl_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET); in dw_pcie_iatu_detect_regions_unroll()
618 dw_pcie_writel_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET, in dw_pcie_iatu_detect_regions_unroll()
621 val = dw_pcie_readl_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET); in dw_pcie_iatu_detect_regions_unroll()
627 pci->num_ib_windows = ib; in dw_pcie_iatu_detect_regions_unroll()
628 pci->num_ob_windows = ob; in dw_pcie_iatu_detect_regions_unroll()
631 static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci) in dw_pcie_iatu_detect_regions() argument
636 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF); in dw_pcie_iatu_detect_regions()
637 max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1; in dw_pcie_iatu_detect_regions()
640 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | i); in dw_pcie_iatu_detect_regions()
641 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000); in dw_pcie_iatu_detect_regions()
642 val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET); in dw_pcie_iatu_detect_regions()
650 dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND | i); in dw_pcie_iatu_detect_regions()
651 dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, 0x11110000); in dw_pcie_iatu_detect_regions()
652 val = dw_pcie_readl_dbi(pci, PCIE_ATU_LOWER_TARGET); in dw_pcie_iatu_detect_regions()
659 pci->num_ib_windows = ib; in dw_pcie_iatu_detect_regions()
660 pci->num_ob_windows = ob; in dw_pcie_iatu_detect_regions()
663 void dw_pcie_iatu_detect(struct dw_pcie *pci) in dw_pcie_iatu_detect() argument
665 struct device *dev = pci->dev; in dw_pcie_iatu_detect()
668 if (pci->version >= 0x480A || (!pci->version && in dw_pcie_iatu_detect()
669 dw_pcie_iatu_unroll_enabled(pci))) { in dw_pcie_iatu_detect()
670 pci->iatu_unroll_enabled = true; in dw_pcie_iatu_detect()
671 if (!pci->atu_base) { in dw_pcie_iatu_detect()
675 pci->atu_size = resource_size(res); in dw_pcie_iatu_detect()
676 pci->atu_base = devm_ioremap_resource(dev, res); in dw_pcie_iatu_detect()
677 if (IS_ERR(pci->atu_base)) in dw_pcie_iatu_detect()
678 pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; in dw_pcie_iatu_detect()
681 if (!pci->atu_size) in dw_pcie_iatu_detect()
683 pci->atu_size = SZ_4K; in dw_pcie_iatu_detect()
685 dw_pcie_iatu_detect_regions_unroll(pci); in dw_pcie_iatu_detect()
687 dw_pcie_iatu_detect_regions(pci); in dw_pcie_iatu_detect()
689 dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? in dw_pcie_iatu_detect()
692 dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound", in dw_pcie_iatu_detect()
693 pci->num_ob_windows, pci->num_ib_windows); in dw_pcie_iatu_detect()
696 void dw_pcie_setup(struct dw_pcie *pci) in dw_pcie_setup() argument
699 struct device *dev = pci->dev; in dw_pcie_setup()
702 if (pci->link_gen > 0) in dw_pcie_setup()
703 dw_pcie_link_set_max_speed(pci, pci->link_gen); in dw_pcie_setup()
706 if (pci->n_fts[0]) { in dw_pcie_setup()
707 val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); in dw_pcie_setup()
709 val |= PORT_AFR_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
710 val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]); in dw_pcie_setup()
711 dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); in dw_pcie_setup()
715 if (pci->n_fts[1]) { in dw_pcie_setup()
716 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); in dw_pcie_setup()
718 val |= pci->n_fts[pci->link_gen - 1]; in dw_pcie_setup()
719 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); in dw_pcie_setup()
722 val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); in dw_pcie_setup()
725 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); in dw_pcie_setup()
727 of_property_read_u32(np, "num-lanes", &pci->num_lanes); in dw_pcie_setup()
728 if (!pci->num_lanes) { in dw_pcie_setup()
729 dev_dbg(pci->dev, "Using h/w default number of lanes\n"); in dw_pcie_setup()
736 switch (pci->num_lanes) { in dw_pcie_setup()
750 dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes); in dw_pcie_setup()
753 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); in dw_pcie_setup()
756 val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); in dw_pcie_setup()
758 switch (pci->num_lanes) { in dw_pcie_setup()
772 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); in dw_pcie_setup()
775 val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); in dw_pcie_setup()
778 dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); in dw_pcie_setup()